From patchwork Sun Apr 15 13:46:06 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7835 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id D1D1C23E47 for ; Sun, 15 Apr 2012 13:46:34 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 7C074A18189 for ; Sun, 15 Apr 2012 13:46:34 +0000 (UTC) Received: by iage36 with SMTP id e36so8543068iag.11 for ; Sun, 15 Apr 2012 06:46:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=LK7mNgsOJtoxWk72l4HRIeWK5Mz1Bwuzem4Kf/A5iBE=; b=ZzETaUtUxFcHG1GgoVvOZIDiafu1JnMM4AWVdrhVcuE7rtK7MSQAQ6Z4RsvNsOqs5P CzG2tPsdkZTY4dlq9T09S9jlCKOl4jEOpSE2N8xqEYv0gf3kUzHussnfdhEwGZdzffAe bW/1BBH01uBce2xRbVCThlZUsket7716+K3kQWa+nnvFQQfeA7UAEf5tK3WXlQ8rNCXO /WcF6Gr0wTr4oeF80EF2NAk63M4nQnIIH/hTU2K3viaSKSmyzIO4U18t8oK/VCCvAF3h cdKldD0e7AMjK8s0HtdsTwA1X9cbrLetwVHKyNs6ZXMgggeR6Tt0dMEOcc/LsavN4E71 PAfw== Received: by 10.50.158.202 with SMTP id ww10mr3052376igb.30.1334497593402; Sun, 15 Apr 2012 06:46:33 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp22196ibj; Sun, 15 Apr 2012 06:46:32 -0700 (PDT) Received: by 10.180.78.164 with SMTP id c4mr6290514wix.10.1334497591867; Sun, 15 Apr 2012 06:46:31 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id c3si4812732wix.29.2012.04.15.06.46.30 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 Apr 2012 06:46:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJPmc-0000Ev-Pr; Sun, 15 Apr 2012 14:46:26 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [PATCH 13/32] target-arm: Convert cp15 c3 register Date: Sun, 15 Apr 2012 14:46:06 +0100 Message-Id: <1334497585-867-14-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> References: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQkaUmHc4NrcABJ4XTR5DJdtS4BOYBQGbZRk7TajMp6gx5ntDEzAvBgtsAWEIZr/w0Hv1iEP Convert the cp15 c3 register (MMU domain access control or MPU write buffer control). NB that this is horribly underdecoded for modern cores (should be crn=3,crm=0, opc1=0,opc2=0) but this change preserves the existing QEMU behaviour. Signed-off-by: Peter Maydell --- target-arm/helper.c | 18 ++++++++++++------ 1 files changed, 12 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 620e652..a682fab 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -61,6 +61,13 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } +static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + env->cp15.c3 = value; + tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */ + return 0; +} + static const ARMCPRegInfo cp_reginfo[] = { /* DBGDIDR: just RAZ. In particular this means the "debug architecture * version" bits will read as a reserved value, which should cause @@ -68,6 +75,11 @@ static const ARMCPRegInfo cp_reginfo[] = { */ { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + /* MMU Domain access control / MPU write buffer control */ + { .name = "DACR", .cp = 15, + .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), + .resetvalue = 0, .writefn = dacr_write }, REGINFO_SENTINEL }; @@ -1539,10 +1551,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) } } break; - case 3: /* MMU Domain access control / MPU write buffer control. */ - env->cp15.c3 = val; - tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */ - break; case 4: /* Reserved. */ goto bad_reg; case 5: /* MMU Fault status / MPU access permission. */ @@ -1930,8 +1938,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) goto bad_reg; } } - case 3: /* MMU Domain access control / MPU write buffer control. */ - return env->cp15.c3; case 4: /* Reserved. */ goto bad_reg; case 5: /* MMU Fault status / MPU access permission. */