From patchwork Sat Apr 14 16:42:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7833 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 1342723E23 for ; Sat, 14 Apr 2012 16:56:53 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id C956BA185C6 for ; Sat, 14 Apr 2012 16:56:52 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so7611950iag.11 for ; Sat, 14 Apr 2012 09:56:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=JKvpPz9Xu0Lo5aJnxEaUn2ORSY3BPEajhh03tf917is=; b=DY0IGmQ5ZYuugMfRRkO99i/anqTePwLTg8HDh6t7T3dEQrS3kPuuZVJrxdC6lrq5cH CB1uXPbBgbxVPmJcuUwZk7RCNKfIh9eBUIGgV6XBhzrGXIB+QSAZD4AZsuLzEVfNlS5h PnWFlEhISD4coE2QP7197q7IsADeYH7JjWW87gpI9FHMK+OGIMfXNaEU4i03xU3nJAKq gBavjKVc09A529G0afQ6232/22e3wCSRxv1VFzdAR8oH9SBobo1qmTmIfAsODOC3Btg+ 78NlQ2EJnmW9dkLjlcNz/Fjt0SSOXOWfFd2Hed/Dr7CFxVj32yTv2rat/mZ/vDfaSwfC k64Q== Received: by 10.50.202.38 with SMTP id kf6mr1542508igc.30.1334422612601; Sat, 14 Apr 2012 09:56:52 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp90788ibj; Sat, 14 Apr 2012 09:56:52 -0700 (PDT) Received: by 10.180.106.9 with SMTP id gq9mr5236940wib.17.1334422611381; Sat, 14 Apr 2012 09:56:51 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id gb7si2365303wib.10.2012.04.14.09.56.50 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 14 Apr 2012 09:56:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJ63M-00086y-ER; Sat, 14 Apr 2012 17:42:24 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook , Anthony Liguori Subject: [PATCH v2 05/14] target-arm: Move CTR setup to per cpu init fns Date: Sat, 14 Apr 2012 17:42:14 +0100 Message-Id: <1334421743-31146-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334421743-31146-1-git-send-email-peter.maydell@linaro.org> References: <1334421743-31146-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlzlSwn+6/1aposLYnD4FG/O0uL45PBO2uQRII242JdPhgXwVoGFx+/eTG42jDduLKgjy4T Move CTR (cache type register) value to an ARMCPU field set up by per-cpu init fns. Signed-off-by: Peter Maydell Acked-by: Andreas Färber --- target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 22 ++++++++++++++++++++++ target-arm/helper.c | 13 +------------ 3 files changed, 24 insertions(+), 12 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index c51eb84..cb9198a 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -73,6 +73,7 @@ typedef struct ARMCPU { uint32_t reset_fpsid; uint32_t mvfr0; uint32_t mvfr1; + uint32_t ctr; } ARMCPU; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 8e2d8c2..9d8247f 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -101,6 +101,7 @@ static void arm926_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP); cpu->midr = ARM_CPUID_ARM926; cpu->reset_fpsid = 0x41011090; + cpu->ctr = 0x1dd20d2; } static void arm946_initfn(Object *obj) @@ -109,6 +110,7 @@ static void arm946_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_MPU); cpu->midr = ARM_CPUID_ARM946; + cpu->ctr = 0x0f004006; } static void arm1026_initfn(Object *obj) @@ -119,6 +121,7 @@ static void arm1026_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_AUXCR); cpu->midr = ARM_CPUID_ARM1026; cpu->reset_fpsid = 0x410110a0; + cpu->ctr = 0x1dd20d2; } static void arm1136_r2_initfn(Object *obj) @@ -130,6 +133,7 @@ static void arm1136_r2_initfn(Object *obj) cpu->reset_fpsid = 0x410120b4; cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; + cpu->ctr = 0x1dd20d2; } static void arm1136_initfn(Object *obj) @@ -142,6 +146,7 @@ static void arm1136_initfn(Object *obj) cpu->reset_fpsid = 0x410120b4; cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; + cpu->ctr = 0x1dd20d2; } static void arm1176_initfn(Object *obj) @@ -154,6 +159,7 @@ static void arm1176_initfn(Object *obj) cpu->reset_fpsid = 0x410120b5; cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; + cpu->ctr = 0x1dd20d2; } static void arm11mpcore_initfn(Object *obj) @@ -166,6 +172,7 @@ static void arm11mpcore_initfn(Object *obj) cpu->reset_fpsid = 0x410120b4; cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; + cpu->ctr = 0x1dd20d2; } static void cortex_m3_initfn(Object *obj) @@ -187,6 +194,7 @@ static void cortex_a8_initfn(Object *obj) cpu->reset_fpsid = 0x410330c0; cpu->mvfr0 = 0x11110222; cpu->mvfr1 = 0x00011100; + cpu->ctr = 0x82048004; } static void cortex_a9_initfn(Object *obj) @@ -206,6 +214,7 @@ static void cortex_a9_initfn(Object *obj) cpu->reset_fpsid = 0x41033090; cpu->mvfr0 = 0x11110222; cpu->mvfr1 = 0x01111111; + cpu->ctr = 0x80038003; } static void cortex_a15_initfn(Object *obj) @@ -223,6 +232,7 @@ static void cortex_a15_initfn(Object *obj) cpu->reset_fpsid = 0x410430f0; cpu->mvfr0 = 0x10110222; cpu->mvfr1 = 0x11111111; + cpu->ctr = 0x8444c004; } static void ti925t_initfn(Object *obj) @@ -231,6 +241,7 @@ static void ti925t_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V4T); set_feature(&cpu->env, ARM_FEATURE_OMAPCP); cpu->midr = ARM_CPUID_TI925T; + cpu->ctr = 0x5109149; } static void sa1100_initfn(Object *obj) @@ -253,6 +264,7 @@ static void pxa250_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA250; + cpu->ctr = 0xd172172; } static void pxa255_initfn(Object *obj) @@ -261,6 +273,7 @@ static void pxa255_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA255; + cpu->ctr = 0xd172172; } static void pxa260_initfn(Object *obj) @@ -269,6 +282,7 @@ static void pxa260_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA260; + cpu->ctr = 0xd172172; } static void pxa261_initfn(Object *obj) @@ -277,6 +291,7 @@ static void pxa261_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA261; + cpu->ctr = 0xd172172; } static void pxa262_initfn(Object *obj) @@ -285,6 +300,7 @@ static void pxa262_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA262; + cpu->ctr = 0xd172172; } static void pxa270a0_initfn(Object *obj) @@ -294,6 +310,7 @@ static void pxa270a0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_A0; + cpu->ctr = 0xd172172; } static void pxa270a1_initfn(Object *obj) @@ -303,6 +320,7 @@ static void pxa270a1_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_A1; + cpu->ctr = 0xd172172; } static void pxa270b0_initfn(Object *obj) @@ -312,6 +330,7 @@ static void pxa270b0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_B0; + cpu->ctr = 0xd172172; } static void pxa270b1_initfn(Object *obj) @@ -321,6 +340,7 @@ static void pxa270b1_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_B1; + cpu->ctr = 0xd172172; } static void pxa270c0_initfn(Object *obj) @@ -330,6 +350,7 @@ static void pxa270c0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_C0; + cpu->ctr = 0xd172172; } static void pxa270c5_initfn(Object *obj) @@ -343,6 +364,7 @@ static void pxa270c5_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); set_feature(&cpu->env, ARM_FEATURE_V7MP); cpu->midr = ARM_CPUID_PXA270_C5; + cpu->ctr = 0xd172172; } static void arm_any_initfn(Object *obj) diff --git a/target-arm/helper.c b/target-arm/helper.c index 777bb03..a23df14 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -50,15 +50,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) { switch (id) { case ARM_CPUID_ARM926: - env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00090078; break; case ARM_CPUID_ARM946: - env->cp15.c0_cachetype = 0x0f004006; env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_ARM1026: - env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00090078; break; case ARM_CPUID_ARM1136: @@ -74,24 +71,20 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) */ memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM1176: memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM11MPCORE: memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x1dd20d2; break; case ARM_CPUID_CORTEXA8: memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x82048004; env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3; env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */ env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */ @@ -101,7 +94,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_CORTEXA9: memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x80038003; env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3; env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */ env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */ @@ -110,7 +102,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_CORTEXA15: memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, cortexa15_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x8444c004; env->cp15.c0_clid = 0x0a200023; env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */ env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */ @@ -123,7 +114,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_TI915T: case ARM_CPUID_TI925T: - env->cp15.c0_cachetype = 0x5109149; env->cp15.c1_sys = 0x00000070; env->cp15.c15_i_max = 0x000; env->cp15.c15_i_min = 0xff0; @@ -134,7 +124,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA261: case ARM_CPUID_PXA262: /* JTAG_ID is ((id << 28) | 0x09265013) */ - env->cp15.c0_cachetype = 0xd172172; env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_PXA270_A0: @@ -145,7 +134,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA270_C5: /* JTAG_ID is ((id << 28) | 0x09265013) */ env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; - env->cp15.c0_cachetype = 0xd172172; env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_SA1100: @@ -184,6 +172,7 @@ void cpu_state_reset(CPUARMState *env) env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; + env->cp15.c0_cachetype = cpu->ctr; #if defined (CONFIG_USER_ONLY) env->uncached_cpsr = ARM_CPU_MODE_USR;