From patchwork Sat Apr 14 16:42:12 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7831 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 65DED23E23 for ; Sat, 14 Apr 2012 16:56:48 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 0BCFBA185C0 for ; Sat, 14 Apr 2012 16:56:47 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so7611950iag.11 for ; Sat, 14 Apr 2012 09:56:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=RKtF+1shk0C117Vxp4HTdZl6e1RxWIq8mNgn6HTBPEs=; b=CnR4G2pRa0uod3qJjgyoyuHdAgLJ5oT81WyowKChwedZ/N3327wS+JM7qIxpB1mtM2 H8SBP+yt910HpJH0C1KqMS8hv2OTlz//wvTUiSGiBoVEQSpNpRLQJPuXDM4LKXhGefWb VwZ04DfmaMM+7UyPjod/nb+HVqJ3ToaD/QwM5kERR61MmOAet75Yd5Vr4Yb7Ku+EgtgS GQAmjJLJ73M4+rz/5XwMSp2I2Z3B0mG8O1RYUIcxHadp28pN8AD9XDtERdcmgb5p25eP z4u+rsQ6suHpzUf3kALSD7FKAxnrfYVu/FGRtQsXUpozGZO0y8mO39eXD1vEFYZD4H/g OfCg== Received: by 10.50.189.232 with SMTP id gl8mr1561877igc.50.1334422607827; Sat, 14 Apr 2012 09:56:47 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp90779ibj; Sat, 14 Apr 2012 09:56:47 -0700 (PDT) Received: by 10.180.95.74 with SMTP id di10mr1498892wib.1.1334422606589; Sat, 14 Apr 2012 09:56:46 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id h2si2382666wiz.2.2012.04.14.09.56.45 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 14 Apr 2012 09:56:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJ63M-00086u-9n; Sat, 14 Apr 2012 17:42:24 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook , Anthony Liguori Subject: [PATCH v2 03/14] target-arm: Move FPSID config to cpu init fns Date: Sat, 14 Apr 2012 17:42:12 +0100 Message-Id: <1334421743-31146-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334421743-31146-1-git-send-email-peter.maydell@linaro.org> References: <1334421743-31146-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQnJOwcflPFSdby8tw/6Wcaz0W6S+WSbcbp5sR5jKgrd6enYNy0xEGFh/eAExchhw8wk5h57 Move the reset FPSID to the ARMCPU struct, and set it in the per-implementation instance init function. At reset we then just copy the reset value into the CPUARMState field. Signed-off-by: Peter Maydell Acked-by: Andreas Färber --- target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 9 +++++++++ target-arm/helper.c | 10 ++-------- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 7e2d4c9..7cc4cd5 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -70,6 +70,7 @@ typedef struct ARMCPU { * prefix means a constant register. */ uint32_t midr; + uint32_t reset_fpsid; } ARMCPU; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 958f5c5..9d23a1a 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -100,6 +100,7 @@ static void arm926_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_VFP); cpu->midr = ARM_CPUID_ARM926; + cpu->reset_fpsid = 0x41011090; } static void arm946_initfn(Object *obj) @@ -117,6 +118,7 @@ static void arm1026_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_AUXCR); cpu->midr = ARM_CPUID_ARM1026; + cpu->reset_fpsid = 0x410110a0; } static void arm1136_r2_initfn(Object *obj) @@ -125,6 +127,7 @@ static void arm1136_r2_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V6); set_feature(&cpu->env, ARM_FEATURE_VFP); cpu->midr = ARM_CPUID_ARM1136_R2; + cpu->reset_fpsid = 0x410120b4; } static void arm1136_initfn(Object *obj) @@ -134,6 +137,7 @@ static void arm1136_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V6); set_feature(&cpu->env, ARM_FEATURE_VFP); cpu->midr = ARM_CPUID_ARM1136; + cpu->reset_fpsid = 0x410120b4; } static void arm1176_initfn(Object *obj) @@ -143,6 +147,7 @@ static void arm1176_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_VAPA); cpu->midr = ARM_CPUID_ARM1176; + cpu->reset_fpsid = 0x410120b5; } static void arm11mpcore_initfn(Object *obj) @@ -152,6 +157,7 @@ static void arm11mpcore_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_VAPA); cpu->midr = ARM_CPUID_ARM11MPCORE; + cpu->reset_fpsid = 0x410120b4; } static void cortex_m3_initfn(Object *obj) @@ -170,6 +176,7 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); cpu->midr = ARM_CPUID_CORTEXA8; + cpu->reset_fpsid = 0x410330c0; } static void cortex_a9_initfn(Object *obj) @@ -186,6 +193,7 @@ static void cortex_a9_initfn(Object *obj) */ set_feature(&cpu->env, ARM_FEATURE_V7MP); cpu->midr = ARM_CPUID_CORTEXA9; + cpu->reset_fpsid = 0x41033090; } static void cortex_a15_initfn(Object *obj) @@ -200,6 +208,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7MP); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); cpu->midr = ARM_CPUID_CORTEXA15; + cpu->reset_fpsid = 0x410430f0; } static void ti925t_initfn(Object *obj) diff --git a/target-arm/helper.c b/target-arm/helper.c index e495de6..3247dd3 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -50,7 +50,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) { switch (id) { case ARM_CPUID_ARM926: - env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090; env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00090078; break; @@ -59,7 +58,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_ARM1026: - env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0; env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00090078; break; @@ -74,7 +72,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) * for 1136_r2 (in particular r0p2 does not actually implement most * of the ID registers). */ - env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -83,7 +80,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM1176: - env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -92,7 +88,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM11MPCORE: - env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -100,7 +95,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_cachetype = 0x1dd20d2; break; case ARM_CPUID_CORTEXA8: - env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100; memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -113,7 +107,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA9: - env->vfp.xregs[ARM_VFP_FPSID] = 0x41033090; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111; memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -125,7 +118,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA15: - env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0; env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222; env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111; memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -201,6 +193,8 @@ void cpu_state_reset(CPUARMState *env) cpu_reset_model_id(env, id); env->cp15.c15_config_base_address = tmp; env->cp15.c0_cpuid = cpu->midr; + env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; + #if defined (CONFIG_USER_ONLY) env->uncached_cpsr = ARM_CPU_MODE_USR; /* For user mode we must enable access to coprocessors */