From patchwork Sat Apr 14 16:42:22 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7827 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 6FA4423E4C for ; Sat, 14 Apr 2012 16:42:38 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 3710DA185C2 for ; Sat, 14 Apr 2012 16:42:38 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so7596947iag.11 for ; Sat, 14 Apr 2012 09:42:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Mo6B7Xujd7pjIu3uzvQgnTwxGvdG7ZS/M0ws+440Ej4=; b=mRHw2m0KSaXxxDBY+2kWSslpZQ/vEDZ1C04qUFghNWngQ0IDiQlu1z/DLCog1voK3u +OQs2LhGsLNvHVLf3072aRnDK2iBaHQJwwA5bK7ma7nsOoSvwfgYheiX2fc09bRN4tJI UOjnSZFpYG/V3OBnHSL+lm3bbNnHjBh7FMWyDysjVeYsC94hF3l+4jprPRUoZ3EIta+s TdTtqCcGJNZKZwMw1zAYkeEXWQz31PqayLK9PH6hMvxbuNJZagphBKEDvoyWGoUhCQvs 1zIV2cUlpQgkxaZoTgRfZF4b+UILtp7eMaNEuYML95tFM6UFWnXBI8iG5iPurc7uOjtS rH5A== Received: by 10.42.179.196 with SMTP id br4mr3499997icb.42.1334421758002; Sat, 14 Apr 2012 09:42:38 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp90382ibj; Sat, 14 Apr 2012 09:42:37 -0700 (PDT) Received: by 10.205.137.15 with SMTP id im15mr1670035bkc.54.1334421755849; Sat, 14 Apr 2012 09:42:35 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id m5si4840711bke.50.2012.04.14.09.42.34 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 14 Apr 2012 09:42:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJ63M-00087E-V2; Sat, 14 Apr 2012 17:42:24 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook , Anthony Liguori Subject: [PATCH v2 13/14] target-arm: Move reset handling to arm_cpu_reset Date: Sat, 14 Apr 2012 17:42:22 +0100 Message-Id: <1334421743-31146-15-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334421743-31146-1-git-send-email-peter.maydell@linaro.org> References: <1334421743-31146-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlxRU0Hv+UCLR0jGgTKyn4a5HnWz4TW+z+3ls+ZDwiULTJruAWCEDFvgWL1nG7SbFWdrx/P Now that cpu_reset_model_id() has gone we can move the reset code over to the class reset function and have cpu_state_reset simply do a reset on the CPU QOM object. Signed-off-by: Peter Maydell Acked-by: Andreas Färber --- target-arm/cpu.c | 94 +++++++++++++++++++++++++++++++++++++++++++++++-- target-arm/helper.c | 97 +-------------------------------------------------- 2 files changed, 92 insertions(+), 99 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 63de462..77347b0 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -20,18 +20,106 @@ #include "cpu-qom.h" #include "qemu-common.h" +#if !defined(CONFIG_USER_ONLY) +#include "hw/loader.h" +#endif /* CPUClass::reset() */ static void arm_cpu_reset(CPUState *s) { ARMCPU *cpu = ARM_CPU(s); ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); + CPUARMState *env = &cpu->env; + uint32_t tmp = 0; + + if (qemu_loglevel_mask(CPU_LOG_RESET)) { + qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); + log_cpu_state(env, 0); + } acc->parent_reset(s); - /* TODO Inline the current contents of cpu_state_reset(), - once cpu_reset_model_id() is eliminated. */ - cpu_state_reset(&cpu->env); + tmp = env->cp15.c15_config_base_address; + memset(env, 0, offsetof(CPUARMState, breakpoints)); + env->cp15.c15_config_base_address = tmp; + env->cp15.c0_cpuid = cpu->midr; + env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; + env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; + env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; + env->cp15.c0_cachetype = cpu->ctr; + env->cp15.c1_sys = cpu->reset_sctlr; + env->cp15.c0_c1[0] = cpu->id_pfr0; + env->cp15.c0_c1[1] = cpu->id_pfr1; + env->cp15.c0_c1[2] = cpu->id_dfr0; + env->cp15.c0_c1[3] = cpu->id_afr0; + env->cp15.c0_c1[4] = cpu->id_mmfr0; + env->cp15.c0_c1[5] = cpu->id_mmfr1; + env->cp15.c0_c1[6] = cpu->id_mmfr2; + env->cp15.c0_c1[7] = cpu->id_mmfr3; + env->cp15.c0_c2[0] = cpu->id_isar0; + env->cp15.c0_c2[1] = cpu->id_isar1; + env->cp15.c0_c2[2] = cpu->id_isar2; + env->cp15.c0_c2[3] = cpu->id_isar3; + env->cp15.c0_c2[4] = cpu->id_isar4; + env->cp15.c0_c2[5] = cpu->id_isar5; + env->cp15.c15_i_min = 0xff0; + env->cp15.c0_clid = cpu->clidr; + memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr)); + + if (arm_feature(env, ARM_FEATURE_IWMMXT)) { + env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; + } + +#if defined(CONFIG_USER_ONLY) + env->uncached_cpsr = ARM_CPU_MODE_USR; + /* For user mode we must enable access to coprocessors */ + env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; + if (arm_feature(env, ARM_FEATURE_IWMMXT)) { + env->cp15.c15_cpar = 3; + } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { + env->cp15.c15_cpar = 1; + } +#else + /* SVC mode with interrupts disabled. */ + env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; + /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is + clear at reset. Initial SP and PC are loaded from ROM. */ + if (IS_M(env)) { + uint32_t pc; + uint8_t *rom; + env->uncached_cpsr &= ~CPSR_I; + rom = rom_ptr(0); + if (rom) { + /* We should really use ldl_phys here, in case the guest + modified flash and reset itself. However images + loaded via -kernel have not been copied yet, so load the + values directly from there. */ + env->regs[13] = ldl_p(rom); + pc = ldl_p(rom + 4); + env->thumb = pc & 1; + env->regs[15] = pc & ~1; + } + } + env->vfp.xregs[ARM_VFP_FPEXC] = 0; + env->cp15.c2_base_mask = 0xffffc000u; + /* v7 performance monitor control register: same implementor + * field as main ID register, and we implement no event counters. + */ + env->cp15.c9_pmcr = (cpu->midr & 0xff000000); +#endif + set_flush_to_zero(1, &env->vfp.standard_fp_status); + set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); + set_default_nan_mode(1, &env->vfp.standard_fp_status); + set_float_detect_tininess(float_tininess_before_rounding, + &env->vfp.fp_status); + set_float_detect_tininess(float_tininess_before_rounding, + &env->vfp.standard_fp_status); + tlb_flush(env, 1); + /* Reset is a state change for some CPUARMState fields which we + * bake assumptions about into translated code, so we need to + * tb_flush(). + */ + tb_flush(env); } static inline void set_feature(CPUARMState *env, int feature) diff --git a/target-arm/helper.c b/target-arm/helper.c index 653885a..101031d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2,106 +2,11 @@ #include "gdbstub.h" #include "helper.h" #include "host-utils.h" -#if !defined(CONFIG_USER_ONLY) -#include "hw/loader.h" -#endif #include "sysemu.h" -/* TODO Move contents into arm_cpu_reset() in cpu.c, - * once cpu_reset_model_id() is eliminated, - * and then forward to cpu_reset() here. - */ void cpu_state_reset(CPUARMState *env) { - uint32_t tmp = 0; - ARMCPU *cpu = arm_env_get_cpu(env); - - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); - log_cpu_state(env, 0); - } - - tmp = env->cp15.c15_config_base_address; - memset(env, 0, offsetof(CPUARMState, breakpoints)); - env->cp15.c15_config_base_address = tmp; - env->cp15.c0_cpuid = cpu->midr; - env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; - env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; - env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; - env->cp15.c0_cachetype = cpu->ctr; - env->cp15.c1_sys = cpu->reset_sctlr; - env->cp15.c0_c1[0] = cpu->id_pfr0; - env->cp15.c0_c1[1] = cpu->id_pfr1; - env->cp15.c0_c1[2] = cpu->id_dfr0; - env->cp15.c0_c1[3] = cpu->id_afr0; - env->cp15.c0_c1[4] = cpu->id_mmfr0; - env->cp15.c0_c1[5] = cpu->id_mmfr1; - env->cp15.c0_c1[6] = cpu->id_mmfr2; - env->cp15.c0_c1[7] = cpu->id_mmfr3; - env->cp15.c0_c2[0] = cpu->id_isar0; - env->cp15.c0_c2[1] = cpu->id_isar1; - env->cp15.c0_c2[2] = cpu->id_isar2; - env->cp15.c0_c2[3] = cpu->id_isar3; - env->cp15.c0_c2[4] = cpu->id_isar4; - env->cp15.c0_c2[5] = cpu->id_isar5; - env->cp15.c15_i_min = 0xff0; - env->cp15.c0_clid = cpu->clidr; - memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr)); - - if (arm_feature(env, ARM_FEATURE_IWMMXT)) { - env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; - } - -#if defined (CONFIG_USER_ONLY) - env->uncached_cpsr = ARM_CPU_MODE_USR; - /* For user mode we must enable access to coprocessors */ - env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; - if (arm_feature(env, ARM_FEATURE_IWMMXT)) { - env->cp15.c15_cpar = 3; - } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { - env->cp15.c15_cpar = 1; - } -#else - /* SVC mode with interrupts disabled. */ - env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; - /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is - clear at reset. Initial SP and PC are loaded from ROM. */ - if (IS_M(env)) { - uint32_t pc; - uint8_t *rom; - env->uncached_cpsr &= ~CPSR_I; - rom = rom_ptr(0); - if (rom) { - /* We should really use ldl_phys here, in case the guest - modified flash and reset itself. However images - loaded via -kernel have not been copied yet, so load the - values directly from there. */ - env->regs[13] = ldl_p(rom); - pc = ldl_p(rom + 4); - env->thumb = pc & 1; - env->regs[15] = pc & ~1; - } - } - env->vfp.xregs[ARM_VFP_FPEXC] = 0; - env->cp15.c2_base_mask = 0xffffc000u; - /* v7 performance monitor control register: same implementor - * field as main ID register, and we implement no event counters. - */ - env->cp15.c9_pmcr = (cpu->midr & 0xff000000); -#endif - set_flush_to_zero(1, &env->vfp.standard_fp_status); - set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); - set_default_nan_mode(1, &env->vfp.standard_fp_status); - set_float_detect_tininess(float_tininess_before_rounding, - &env->vfp.fp_status); - set_float_detect_tininess(float_tininess_before_rounding, - &env->vfp.standard_fp_status); - tlb_flush(env, 1); - /* Reset is a state change for some CPUARMState fields which we - * bake assumptions about into translated code, so we need to - * tb_flush(). - */ - tb_flush(env); + cpu_reset(ENV_GET_CPU(env)); } static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)