From patchwork Sat Apr 14 16:42:21 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7829 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 6B01523E4C for ; Sat, 14 Apr 2012 16:43:13 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 31A21A185C2 for ; Sat, 14 Apr 2012 16:43:13 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so7596938iag.11 for ; Sat, 14 Apr 2012 09:43:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=dAeenvo7+FZ2sFyZYo+tgmCMN5ewovxAgkp5FF822EI=; b=nAw2UDWyZzIMOIeompes2mLEagF+LXi4REmkjTkst+FwWJ71q/TaZ/92uLN2kVOVPG mLpFfBqRo05dqlmsb9jI5KKNipqI194z8mNCCS4wIjlunNl2HW3Tvjbz8Ub1/fPSrcHS mLsrHePUkNlengd6cq/1/WHLPDcT+SH99Q4UF1LWYHTKKzeJqATdXsVC5BdHdJTvbETw VY3w04wz7kWkLjryIGn1XhtG6MvamRKMyy/UTW5ahj/i2RNyBkDgdQ50VN+owwRu9jXm BwbxTElthkZ112VvoyKDvgk2WlfkLPNjkY38hSAovzg11bsthbNkTwLIaUFIEVACOa2q 6wuw== Received: by 10.50.202.38 with SMTP id kf6mr1521484igc.30.1334421792988; Sat, 14 Apr 2012 09:43:12 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp90400ibj; Sat, 14 Apr 2012 09:43:12 -0700 (PDT) Received: by 10.68.235.2 with SMTP id ui2mr14080554pbc.30.1334421792307; Sat, 14 Apr 2012 09:43:12 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id or9si2588043pbb.67.2012.04.14.09.43.11 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 14 Apr 2012 09:43:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJ63M-00087C-Sq; Sat, 14 Apr 2012 17:42:24 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook , Anthony Liguori Subject: [PATCH v2 12/14] target-arm: Drop cpu_reset_model_id() Date: Sat, 14 Apr 2012 17:42:21 +0100 Message-Id: <1334421743-31146-14-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334421743-31146-1-git-send-email-peter.maydell@linaro.org> References: <1334421743-31146-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQmFLz48v2SEGGLZXGpU9lw5rN8OuIn9vgx37kYliCls6o65f0KfJiUzpkJUYAUBW0BLpDvC cpu_reset_model_id() is now empty and we can remove it. Signed-off-by: Peter Maydell Acked-by: Andreas Färber --- target-arm/helper.c | 59 +-------------------------------------------------- 1 files changed, 1 insertions(+), 58 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 5cbc7e0..653885a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -7,66 +7,12 @@ #endif #include "sysemu.h" -static void cpu_reset_model_id(CPUARMState *env, uint32_t id) -{ - switch (id) { - case ARM_CPUID_ARM926: - break; - case ARM_CPUID_ARM946: - break; - case ARM_CPUID_ARM1026: - break; - case ARM_CPUID_ARM1136: - /* This is the 1136 r1, which is a v6K core */ - case ARM_CPUID_ARM1136_R2: - break; - case ARM_CPUID_ARM1176: - break; - case ARM_CPUID_ARM11MPCORE: - break; - case ARM_CPUID_CORTEXA8: - break; - case ARM_CPUID_CORTEXA9: - break; - case ARM_CPUID_CORTEXA15: - break; - case ARM_CPUID_CORTEXM3: - break; - case ARM_CPUID_ANY: /* For userspace emulation. */ - break; - case ARM_CPUID_TI915T: - case ARM_CPUID_TI925T: - break; - case ARM_CPUID_PXA250: - case ARM_CPUID_PXA255: - case ARM_CPUID_PXA260: - case ARM_CPUID_PXA261: - case ARM_CPUID_PXA262: - break; - case ARM_CPUID_PXA270_A0: - case ARM_CPUID_PXA270_A1: - case ARM_CPUID_PXA270_B0: - case ARM_CPUID_PXA270_B1: - case ARM_CPUID_PXA270_C0: - case ARM_CPUID_PXA270_C5: - break; - case ARM_CPUID_SA1100: - case ARM_CPUID_SA1110: - break; - default: - cpu_abort(env, "Bad CPU ID: %x\n", id); - break; - } - -} - /* TODO Move contents into arm_cpu_reset() in cpu.c, * once cpu_reset_model_id() is eliminated, * and then forward to cpu_reset() here. */ void cpu_state_reset(CPUARMState *env) { - uint32_t id; uint32_t tmp = 0; ARMCPU *cpu = arm_env_get_cpu(env); @@ -75,11 +21,8 @@ void cpu_state_reset(CPUARMState *env) log_cpu_state(env, 0); } - id = cpu->midr; tmp = env->cp15.c15_config_base_address; memset(env, 0, offsetof(CPUARMState, breakpoints)); - if (id) - cpu_reset_model_id(env, id); env->cp15.c15_config_base_address = tmp; env->cp15.c0_cpuid = cpu->midr; env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; @@ -144,7 +87,7 @@ void cpu_state_reset(CPUARMState *env) /* v7 performance monitor control register: same implementor * field as main ID register, and we implement no event counters. */ - env->cp15.c9_pmcr = (id & 0xff000000); + env->cp15.c9_pmcr = (cpu->midr & 0xff000000); #endif set_flush_to_zero(1, &env->vfp.standard_fp_status); set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);