From patchwork Sat Apr 14 16:42:19 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7826 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id DFD6623E4C for ; Sat, 14 Apr 2012 16:42:37 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id A427CA185C2 for ; Sat, 14 Apr 2012 16:42:37 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so7596938iag.11 for ; Sat, 14 Apr 2012 09:42:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=S4IufU1bh0rDVY5kS4AlvBy9zTDQ4Dx1kzWA6kb4HI0=; b=TXCR53xt6HNqdnH3X8K4lFCvXhCAWbJxLu6Tav+HP8VEo7f8Iu0dUwpF3adgQR/9df oXbNSPOnOijADPkt/eWqSuPGpwkyIYt6ioQRAsqkK3y7FLj+CVmTKwUuPLeBJNQqHqdg nCuD4uycMhCML3he99lVFevOpKEPO8iwQ2Kq0+X8BQqIuN35fphXjCN6C91zZ0Epy9oq 2CXzbZSNYsUV1wrHyGfVx34GYAWRS7ZtRu4k2gkoi9+d6cKMP1O2zXtkLMs3DKK46ujO 5+4CdUrVm5BbUItzldhTN5Yd3PYW/vRFjdKZGH4YeCNm+sScrytI70E5LhJA6cGRURfV o5bg== Received: by 10.50.242.5 with SMTP id wm5mr1555814igc.40.1334421757469; Sat, 14 Apr 2012 09:42:37 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp90381ibj; Sat, 14 Apr 2012 09:42:36 -0700 (PDT) Received: by 10.216.144.138 with SMTP id n10mr3292945wej.56.1334421755709; Sat, 14 Apr 2012 09:42:35 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id k8si13068716wed.98.2012.04.14.09.42.34 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 14 Apr 2012 09:42:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJ63M-000878-PD; Sat, 14 Apr 2012 17:42:24 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook , Anthony Liguori Subject: [PATCH v2 10/14] target-arm: Move OMAP cp15_i_{max, min} reset to cpu_state_reset Date: Sat, 14 Apr 2012 17:42:19 +0100 Message-Id: <1334421743-31146-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334421743-31146-1-git-send-email-peter.maydell@linaro.org> References: <1334421743-31146-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQl8olmCslLTKECfw7SQ3BL08Y6t3olvpNryYcTSqg4TCYri/vqfNxwjyYMA0Du9KtvoOiME Move the OMAP-specific cp15_i_{max,min} reset to cpu_state_reset; since these registers are only accessible on CPUs with the OMAPCP feature set there's no need to guard this reset with either a CPUID or feature bit check. Signed-off-by: Peter Maydell Reviewed-by: Andreas Färber --- target-arm/helper.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 84830ff..fb618a7 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -47,8 +47,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_TI915T: case ARM_CPUID_TI925T: - env->cp15.c15_i_max = 0x000; - env->cp15.c15_i_min = 0xff0; break; case ARM_CPUID_PXA250: case ARM_CPUID_PXA255: @@ -114,6 +112,7 @@ void cpu_state_reset(CPUARMState *env) env->cp15.c0_c2[3] = cpu->id_isar3; env->cp15.c0_c2[4] = cpu->id_isar4; env->cp15.c0_c2[5] = cpu->id_isar5; + env->cp15.c15_i_min = 0xff0; if (arm_feature(env, ARM_FEATURE_IWMMXT)) { env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';