From patchwork Sat Apr 14 16:42:17 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7822 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 05ABA23E4C for ; Sat, 14 Apr 2012 16:42:32 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id C0BE9A185B8 for ; Sat, 14 Apr 2012 16:42:31 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so7596938iag.11 for ; Sat, 14 Apr 2012 09:42:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Cj6d55gg07XsJpPWwDVtlcslxJ58+clYuPENopfWOZ8=; b=ZC1sle162QdNPbiW856XNqqietU6IcYyhTR1q3yuXFyuw2R8+Vex4FbL3KVwM69n81 8ev68GJqQFFSS/hXRvdMteaEt+qOQ1BkyaE+ctd7iGmRo7r0FTfdF0teyPGkfHPZaerl UwjwMTw/vTkEJCmeh8HglaSYCokEpKcey/M+OVVumNxWiBRTKog9XqEXO2r0b7oHMaGl xIs6OJsUycxgjwDn7Tw7EVj3pEGBo0X1eZKlEf8o/JAOcUk5ERq6z02kufV3r/H7nLDc 4OazEYRio452QxMEdmxr6vM1CzurVzVJDbjVhdKkWqijRGgXQconzUvbRhhzPzY69Ckm ODDg== Received: by 10.50.158.202 with SMTP id ww10mr1516559igb.30.1334421751575; Sat, 14 Apr 2012 09:42:31 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp90366ibj; Sat, 14 Apr 2012 09:42:30 -0700 (PDT) Received: by 10.205.133.210 with SMTP id hz18mr1604327bkc.117.1334421749396; Sat, 14 Apr 2012 09:42:29 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id ul4si4833095bkb.77.2012.04.14.09.42.28 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 14 Apr 2012 09:42:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJ63M-000874-LC; Sat, 14 Apr 2012 17:42:24 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook , Anthony Liguori Subject: [PATCH v2 08/14] target-arm: Move iWMMXT wCID reset to cpu_state_reset Date: Sat, 14 Apr 2012 17:42:17 +0100 Message-Id: <1334421743-31146-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334421743-31146-1-git-send-email-peter.maydell@linaro.org> References: <1334421743-31146-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlmb6Qt8KRHPrEeMrkDAMORX6T7kgiGdlP2jDlZJIKlE1huiGa5a64UHIxKiSpkEQUpRfA+ Move the iWMMXT wCID reset to cpu_state_reset(). Since we use the same value for all CPUs with this feature (with the major/minor revision fields set to the QEMU specific 'Q' value) there's no need to create an ARMCPU field just for this. Signed-off-by: Peter Maydell Reviewed-by: Andreas Färber --- target-arm/helper.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 3e31f94..319614a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -121,7 +121,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA270_B1: case ARM_CPUID_PXA270_C0: case ARM_CPUID_PXA270_C5: - env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; break; case ARM_CPUID_SA1100: case ARM_CPUID_SA1110: @@ -161,6 +160,10 @@ void cpu_state_reset(CPUARMState *env) env->cp15.c0_cachetype = cpu->ctr; env->cp15.c1_sys = cpu->reset_sctlr; + if (arm_feature(env, ARM_FEATURE_IWMMXT)) { + env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; + } + #if defined (CONFIG_USER_ONLY) env->uncached_cpsr = ARM_CPU_MODE_USR; /* For user mode we must enable access to coprocessors */