From patchwork Wed Apr 4 15:30:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7619 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id D6C8023F90 for ; Wed, 4 Apr 2012 15:31:11 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id 83F81A180D2 for ; Wed, 4 Apr 2012 15:31:11 +0000 (UTC) Received: by yhpp61 with SMTP id p61so272154yhp.11 for ; Wed, 04 Apr 2012 08:31:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=2+6u0ipOY4prcL0BLBrf68ahYniT54b5lUY2+PbSImk=; b=SkmFFnP2QTWmWjeVM86jgXKAeQ95R4b6Q+3DWsLYDT/pzwYTBYFR31yYURD98MVHBY w7+FKqzxFACidFMPwpaYHZ7W8r+Zf13tspaAxd45E6gqNJ0hAeP+q8Ni2orP0Y6mQOoH DMn6bkxiItaqOd8tC+8bObE5b6oG+w+bG+8U7O++YUsqZDlngZpDfIuVoMRxxWS8sj/0 3/K87csNbWgSzsN4v0RklfZiSYZDFhkbazqzFzeDwHwGqQAHJMrfnGxfU5/Y89uBuCIi P1EYX6oCJywQSAu2jxmC7yABiEgJGchxH07ueQq9F2iG3JqgQL7w2Z/qjAjfk4AKLOME 3b9Q== Received: by 10.50.51.197 with SMTP id m5mr2055707igo.38.1333553470323; Wed, 04 Apr 2012 08:31:10 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.164.217 with SMTP id f25csp45097iby; Wed, 4 Apr 2012 08:31:08 -0700 (PDT) Received: by 10.216.135.223 with SMTP id u73mr1673191wei.117.1333553466819; Wed, 04 Apr 2012 08:31:06 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id r59si1149834weq.49.2012.04.04.08.31.06 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 04 Apr 2012 08:31:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SFSAp-0003IQ-2N; Wed, 04 Apr 2012 16:31:03 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: Paul Brook , Evgeny Voevodin , patches@linaro.org Subject: [PATCH 06/13] hw/a9mpcore.c: Switch to using sysbus GIC Date: Wed, 4 Apr 2012 16:30:55 +0100 Message-Id: <1333553462-12633-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1333553462-12633-1-git-send-email-peter.maydell@linaro.org> References: <1333553462-12633-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlpYNWkNN/9J9hNj0NtGJHLfSYqZRK92DhzFvZOC/EJRo+6GGwIYD/cLiP8tG1uaYCeN3Kn Switch the a9mpcore to using the sysbus GIC device rather than having the a9mp private memory region device subclass the GIC. Signed-off-by: Peter Maydell --- hw/a9mpcore.c | 60 +++++++++++++++++++++++++++++++++----------------------- 1 files changed, 35 insertions(+), 25 deletions(-) diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c index 164a0d3..c2ff74d 100644 --- a/hw/a9mpcore.c +++ b/hw/a9mpcore.c @@ -10,22 +10,19 @@ #include "sysbus.h" -#define LEGACY_INCLUDED_GIC -#include "arm_gic.c" - /* A9MP private memory region. */ typedef struct a9mp_priv_state { - gic_state gic; + SysBusDevice busdev; uint32_t scu_control; uint32_t scu_status; uint32_t old_timer_status[8]; uint32_t num_cpu; - qemu_irq *timer_irq; MemoryRegion scu_iomem; MemoryRegion ptimer_iomem; MemoryRegion container; DeviceState *mptimer; + DeviceState *gic; uint32_t num_irq; } a9mp_priv_state; @@ -114,18 +111,9 @@ static const MemoryRegionOps a9_scu_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static void a9mpcore_timer_irq_handler(void *opaque, int irq, int level) -{ - a9mp_priv_state *s = (a9mp_priv_state *)opaque; - if (level && !s->old_timer_status[irq]) { - gic_set_pending_private(&s->gic, irq >> 1, 29 + (irq & 1)); - } - s->old_timer_status[irq] = level; -} - static void a9mp_priv_reset(DeviceState *dev) { - a9mp_priv_state *s = FROM_SYSBUSGIC(a9mp_priv_state, sysbus_from_qdev(dev)); + a9mp_priv_state *s = FROM_SYSBUS(a9mp_priv_state, sysbus_from_qdev(dev)); int i; s->scu_control = 0; for (i = 0; i < ARRAY_SIZE(s->old_timer_status); i++) { @@ -133,13 +121,29 @@ static void a9mp_priv_reset(DeviceState *dev) } } +static void a9mp_priv_set_irq(void *opaque, int irq, int level) +{ + a9mp_priv_state *s = (a9mp_priv_state *)opaque; + qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); +} + static int a9mp_priv_init(SysBusDevice *dev) { - a9mp_priv_state *s = FROM_SYSBUSGIC(a9mp_priv_state, dev); - SysBusDevice *busdev; + a9mp_priv_state *s = FROM_SYSBUS(a9mp_priv_state, dev); + SysBusDevice *busdev, *gicbusdev; int i; - gic_init(&s->gic, s->num_cpu, s->num_irq); + s->gic = qdev_create(NULL, "arm_gic"); + qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); + qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); + qdev_init_nofail(s->gic); + gicbusdev = sysbus_from_qdev(s->gic); + + /* Pass through outbound IRQ lines from the GIC */ + sysbus_pass_irq(dev, gicbusdev); + + /* Pass through inbound GPIO lines to the GIC */ + qdev_init_gpio_in(&s->busdev.qdev, a9mp_priv_set_irq, s->num_irq - 32); s->mptimer = qdev_create(NULL, "arm_mptimer"); qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); @@ -161,7 +165,8 @@ static int a9mp_priv_init(SysBusDevice *dev) memory_region_init_io(&s->scu_iomem, &a9_scu_ops, s, "a9mp-scu", 0x100); memory_region_add_subregion(&s->container, 0, &s->scu_iomem); /* GIC CPU interface */ - memory_region_add_subregion(&s->container, 0x100, &s->gic.cpuiomem[0]); + memory_region_add_subregion(&s->container, 0x100, + sysbus_mmio_get_region(gicbusdev, 1)); /* Note that the A9 exposes only the "timer/watchdog for this core" * memory region, not the "timer/watchdog for core X" ones 11MPcore has. */ @@ -169,15 +174,20 @@ static int a9mp_priv_init(SysBusDevice *dev) sysbus_mmio_get_region(busdev, 0)); memory_region_add_subregion(&s->container, 0x620, sysbus_mmio_get_region(busdev, 1)); - memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem); + memory_region_add_subregion(&s->container, 0x1000, + sysbus_mmio_get_region(gicbusdev, 0)); sysbus_init_mmio(dev, &s->container); - /* Wire up the interrupt from each watchdog and timer. */ - s->timer_irq = qemu_allocate_irqs(a9mpcore_timer_irq_handler, - s, (s->num_cpu + 1) * 2); - for (i = 0; i < s->num_cpu * 2; i++) { - sysbus_connect_irq(busdev, i, s->timer_irq[i]); + /* Wire up the interrupt from each watchdog and timer. + * For each core the timer is PPI 29 and the watchdog PPI 30. + */ + for (i = 0; i < s->num_cpu; i++) { + int ppibase = (s->num_irq - 32) + i * 32; + sysbus_connect_irq(busdev, i * 2, + qdev_get_gpio_in(s->gic, ppibase + 29)); + sysbus_connect_irq(busdev, i * 2 + 1, + qdev_get_gpio_in(s->gic, ppibase + 30)); } return 0; }