From patchwork Wed Apr 4 15:30:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7626 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 4C80123E5B for ; Wed, 4 Apr 2012 15:31:36 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 1428EA180D2 for ; Wed, 4 Apr 2012 15:31:35 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so623238iag.11 for ; Wed, 04 Apr 2012 08:31:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=ZRNrcYDWB0vp0ndgyaqaRtO7/MbHbfWPaa2JZPFpylY=; b=VPX+BQcbqfDKQx9s8gBv5sbGGh2CXOi+yKmGflnAyxlHHp8Bgr12IA+Ikhm0pRpKpu 664gRFXFq4THR5cF9XhTi919QMQiYj1FIvBpWeoXT+5wO4ynajc3dodprQV65tV7sJUR mT6S++UFlBdydDNNx+ay+pV2dwLmnTed/Jt+yEtM7dNgGQZrEETTFFhSt8cvKvbvotyM TZvcaP13glWIPCCTaBfbZJ9jzejda6SFki8Ep+jZkfdgA3/kMcSed4VQ2OuNVs1CH7YS tfnbLxouilr93i44LlnkeENNKN6ZmcDumtdo4jJxiBvsEpy01QixCp7xZPvFtxi4Td/d NKZg== Received: by 10.42.155.9 with SMTP id s9mr10213052icw.51.1333553495842; Wed, 04 Apr 2012 08:31:35 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.164.217 with SMTP id f25csp45125iby; Wed, 4 Apr 2012 08:31:35 -0700 (PDT) Received: by 10.180.101.230 with SMTP id fj6mr6403635wib.13.1333553494388; Wed, 04 Apr 2012 08:31:34 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id r3si2566240wic.47.2012.04.04.08.31.33 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 04 Apr 2012 08:31:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SFSAo-0003IO-TB; Wed, 04 Apr 2012 16:31:02 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: Paul Brook , Evgeny Voevodin , patches@linaro.org Subject: [PATCH 05/13] hw/a15mpcore: switch to using sysbus GIC Date: Wed, 4 Apr 2012 16:30:54 +0100 Message-Id: <1333553462-12633-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1333553462-12633-1-git-send-email-peter.maydell@linaro.org> References: <1333553462-12633-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQkUXxPt74YX6nD8VDiiCoUAQhz4crGutOKri5Y2ugMzyoAAFfR11vpHa1jSWNCDfj/UyTrm Switch the a15mpcore private peripheral region to using the standalone sysbus GIC device. Signed-off-by: Peter Maydell --- hw/a15mpcore.c | 35 ++++++++++++++++++++++++++--------- 1 files changed, 26 insertions(+), 9 deletions(-) diff --git a/hw/a15mpcore.c b/hw/a15mpcore.c index 54c0dbf..5a7b365 100644 --- a/hw/a15mpcore.c +++ b/hw/a15mpcore.c @@ -20,23 +20,38 @@ #include "sysbus.h" -#define LEGACY_INCLUDED_GIC -#include "arm_gic.c" - /* A15MP private memory region. */ typedef struct A15MPPrivState { - gic_state gic; + SysBusDevice busdev; uint32_t num_cpu; uint32_t num_irq; MemoryRegion container; + DeviceState *gic; } A15MPPrivState; +static void a15mp_priv_set_irq(void *opaque, int irq, int level) +{ + A15MPPrivState *s = (A15MPPrivState *)opaque; + qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); +} + static int a15mp_priv_init(SysBusDevice *dev) { - A15MPPrivState *s = FROM_SYSBUSGIC(A15MPPrivState, dev); + A15MPPrivState *s = FROM_SYSBUS(A15MPPrivState, dev); + SysBusDevice *busdev; + + s->gic = qdev_create(NULL, "arm_gic"); + qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); + qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); + qdev_init_nofail(s->gic); + busdev = sysbus_from_qdev(s->gic); + + /* Pass through outbound IRQ lines from the GIC */ + sysbus_pass_irq(dev, busdev); - gic_init(&s->gic, s->num_cpu, s->num_irq); + /* Pass through inbound GPIO lines to the GIC */ + qdev_init_gpio_in(&s->busdev.qdev, a15mp_priv_set_irq, s->num_irq - 32); /* Memory map (addresses are offsets from PERIPHBASE): * 0x0000-0x0fff -- reserved @@ -47,8 +62,10 @@ static int a15mp_priv_init(SysBusDevice *dev) * 0x6000-0x7fff -- GIC virtual CPU interface (not modelled) */ memory_region_init(&s->container, "a15mp-priv-container", 0x8000); - memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem); - memory_region_add_subregion(&s->container, 0x2000, &s->gic.cpuiomem[0]); + memory_region_add_subregion(&s->container, 0x1000, + sysbus_mmio_get_region(busdev, 0)); + memory_region_add_subregion(&s->container, 0x2000, + sysbus_mmio_get_region(busdev, 1)); sysbus_init_mmio(dev, &s->container); return 0; @@ -72,7 +89,7 @@ static void a15mp_priv_class_init(ObjectClass *klass, void *data) SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); k->init = a15mp_priv_init; dc->props = a15mp_priv_properties; - /* We currently have no savable state outside the common GIC state */ + /* We currently have no savable state */ } static TypeInfo a15mp_priv_info = {