From patchwork Wed Apr 4 15:30:53 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7617 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 5A36B23E5B for ; Wed, 4 Apr 2012 15:31:10 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id EDBECA180D2 for ; Wed, 4 Apr 2012 15:31:09 +0000 (UTC) Received: by iage36 with SMTP id e36so623238iag.11 for ; Wed, 04 Apr 2012 08:31:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=kOeg4unz54tTfiuopGIPRQ2/8XVr06oDIAKd/6BraCw=; b=RW8+S/Hp8spcmrdNC811bpjYNa4kmItJpNsiDarRBkKIcnK7tjlZ4xC+ViglxYeDX8 9BPiplGht3804YMr+LhQlLkVgeMjwe2GW/gaPu5fK+lcWnU9xqMxMjyGK9GiHLOL5Z53 37V5OdgDgQHrL2v9h/9TQCejP0RYmZObXh8AjAusj0DFEuh1OoeVRZJKHFBakJlUs7uv Gw/GWsYFgBhHIFTDhDziuCi/BPUYah7Au3V29BJmSJxd9VsrXooR6lB3m+a/3iK445D6 p0vxjM7LbyVH11Ic8/MS4vdfMRsL9MIIfpUSC4wc7r823TvncwwYQwJzw2QBrwMZWxE6 4/Tg== Received: by 10.50.168.67 with SMTP id zu3mr2067366igb.28.1333553469128; Wed, 04 Apr 2012 08:31:09 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.164.217 with SMTP id f25csp45096iby; Wed, 4 Apr 2012 08:31:08 -0700 (PDT) Received: by 10.180.107.104 with SMTP id hb8mr6297729wib.8.1333553467024; Wed, 04 Apr 2012 08:31:07 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id c7si1317865wia.20.2012.04.04.08.31.06 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 04 Apr 2012 08:31:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SFSAo-0003IM-Qm; Wed, 04 Apr 2012 16:31:02 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: Paul Brook , Evgeny Voevodin , patches@linaro.org Subject: [PATCH 04/13] arm_gic: Make the GIC its own sysbus device Date: Wed, 4 Apr 2012 16:30:53 +0100 Message-Id: <1333553462-12633-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1333553462-12633-1-git-send-email-peter.maydell@linaro.org> References: <1333553462-12633-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQmD2ATLmLlRVNw5dsedjX4xufxnQ3QqpJqd/3a9l4G/WJsp9PZ2ILT1MKLP27loM6okkjyZ Compile arm_gic.c as a standalone C file to produce a self contained sysbus GIC device. Support the legacy usage by #include of the .c file by making those users #define LEGACY_INCLUDED_GIC, so we can convert them one by one. Signed-off-by: Peter Maydell Reviewed-by: Evgeny Voevodin --- Makefile.target | 1 + hw/a15mpcore.c | 1 + hw/a9mpcore.c | 1 + hw/arm11mpcore.c | 1 + hw/arm_gic.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++++++- hw/armv7m_nvic.c | 1 + hw/exynos4210_gic.c | 1 + hw/realview_gic.c | 1 + 8 files changed, 57 insertions(+), 1 deletions(-) diff --git a/Makefile.target b/Makefile.target index cff15f0..0d605d8 100644 --- a/Makefile.target +++ b/Makefile.target @@ -364,6 +364,7 @@ obj-arm-y += cadence_uart.o obj-arm-y += cadence_ttc.o obj-arm-y += cadence_gem.o obj-arm-y += xilinx_zynq.o zynq_slcr.o +obj-arm-y += arm_gic.o obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o obj-arm-y += exynos4210_gic.o exynos4210_combiner.o exynos4210.o obj-arm-y += exynos4_boards.o exynos4210_uart.o exynos4210_pwm.o diff --git a/hw/a15mpcore.c b/hw/a15mpcore.c index 2e2ed42..54c0dbf 100644 --- a/hw/a15mpcore.c +++ b/hw/a15mpcore.c @@ -20,6 +20,7 @@ #include "sysbus.h" +#define LEGACY_INCLUDED_GIC #include "arm_gic.c" /* A15MP private memory region. */ diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c index 1d83c37..164a0d3 100644 --- a/hw/a9mpcore.c +++ b/hw/a9mpcore.c @@ -10,6 +10,7 @@ #include "sysbus.h" +#define LEGACY_INCLUDED_GIC #include "arm_gic.c" /* A9MP private memory region. */ diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c index c4829d8..e876a0e 100644 --- a/hw/arm11mpcore.c +++ b/hw/arm11mpcore.c @@ -10,6 +10,7 @@ #include "sysbus.h" #include "qemu-timer.h" +#define LEGACY_INCLUDED_GIC #include "arm_gic.c" /* MPCore private memory region. */ diff --git a/hw/arm_gic.c b/hw/arm_gic.c index fabbcc5..b0b6ec5 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -11,6 +11,8 @@ controller, MPCore distributed interrupt controller and ARMv7-M Nested Vectored Interrupt Controller. */ +#include "sysbus.h" + /* Maximum number of possible interrupts, determined by the GIC architecture */ #define GIC_MAXIRQ 1020 /* First 32 are private to each CPU (SGIs and PPIs). */ @@ -112,7 +114,7 @@ typedef struct gic_state int current_pending[NCPU]; #if NCPU > 1 - int num_cpu; + uint32_t num_cpu; #endif MemoryRegion iomem; /* Distributor */ @@ -906,3 +908,50 @@ static void gic_init(gic_state *s, int num_irq) gic_reset(s); register_savevm(NULL, "arm_gic", -1, 2, gic_save, gic_load, s); } + +#ifndef LEGACY_INCLUDED_GIC + +static int arm_gic_init(SysBusDevice *dev) +{ + /* Device instance init function for the GIC sysbus device */ + int i; + gic_state *s = FROM_SYSBUS(gic_state, dev); + gic_init(s, s->num_cpu, s->num_irq); + /* Distributor */ + sysbus_init_mmio(dev, &s->iomem); + /* cpu interfaces (one for "current cpu" plus one per cpu) */ + for (i = 0; i <= NUM_CPU(s); i++) { + sysbus_init_mmio(dev, &s->cpuiomem[i]); + } + return 0; +} + +static Property arm_gic_properties[] = { + DEFINE_PROP_UINT32("num-cpu", gic_state, num_cpu, 1), + DEFINE_PROP_UINT32("num-irq", gic_state, num_irq, 32), +}; + +static void arm_gic_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); + sbc->init = arm_gic_init; + dc->props = arm_gic_properties; + dc->no_user = 1; +} + +static TypeInfo arm_gic_info = { + .name = "arm_gic", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(gic_state), + .class_init = arm_gic_class_init, +}; + +static void arm_gic_register_types(void) +{ + type_register_static(&arm_gic_info); +} + +type_init(arm_gic_register_types) + +#endif diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index 99ed85b..79cf448 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -16,6 +16,7 @@ #include "exec-memory.h" #define NVIC 1 +#define LEGACY_INCLUDED_GIC static uint32_t nvic_readl(void *opaque, uint32_t offset); static void nvic_writel(void *opaque, uint32_t offset, uint32_t value); diff --git a/hw/exynos4210_gic.c b/hw/exynos4210_gic.c index ff7ab84..a05dab2 100644 --- a/hw/exynos4210_gic.c +++ b/hw/exynos4210_gic.c @@ -262,6 +262,7 @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) /********* GIC part *********/ +#define LEGACY_INCLUDED_GIC #include "arm_gic.c" typedef struct { diff --git a/hw/realview_gic.c b/hw/realview_gic.c index aa780fe..a3b5a04 100644 --- a/hw/realview_gic.c +++ b/hw/realview_gic.c @@ -9,6 +9,7 @@ #include "sysbus.h" +#define LEGACY_INCLUDED_GIC #include "arm_gic.c" typedef struct {