From patchwork Wed Apr 4 15:30:52 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7629 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 374D523ED2 for ; Wed, 4 Apr 2012 15:56:50 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id A9F97A180DB for ; Wed, 4 Apr 2012 15:56:49 +0000 (UTC) Received: by iage36 with SMTP id e36so665063iag.11 for ; Wed, 04 Apr 2012 08:56:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=TqniGK3z6ERCyd2tYhG6xEDjy1F50kNlZkZeILZTb5U=; b=QyBjuG4ae8JUTfIIIQPx5HQIbSkbGi8JJ9QixYy7JkL6Bh/ibTHqNBEJ8Tkm+yPFCz HE61N0E55MCKOqsi6mF748mXEPwo6Qw+dhkCnjv0mBLSriGkwFubHgReyvPqagYuqRnL YPsKWUDkFbZonZp76K452ziUlYkde7uH30ByFX/B0T5CNJ+e1+BEASeMfMVKeLI5iVTC WqCQhsxgmqcLdpK5zGJRheln4HgzSW6V7rAag3jpQoqfwB/oVfSerHueH5pDRit58WsT UXz3R0Cr1yUoL76hWUEnQyBQqiIW50/5iHqLczYkH86PBqF8W2jcHkxGZ3hU7lM0hN5E PmHQ== Received: by 10.42.203.148 with SMTP id fi20mr10285868icb.10.1333555009129; Wed, 04 Apr 2012 08:56:49 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.164.217 with SMTP id f25csp46438iby; Wed, 4 Apr 2012 08:56:48 -0700 (PDT) Received: by 10.216.135.97 with SMTP id t75mr1712574wei.60.1333555007195; Wed, 04 Apr 2012 08:56:47 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id gg1si1396596wib.43.2012.04.04.08.56.46 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 04 Apr 2012 08:56:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SFSAo-0003IK-OB; Wed, 04 Apr 2012 16:31:02 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: Paul Brook , Evgeny Voevodin , patches@linaro.org Subject: [PATCH 03/13] hw/arm_gic.c: Expose PPI inputs as gpio inputs Date: Wed, 4 Apr 2012 16:30:52 +0100 Message-Id: <1333553462-12633-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1333553462-12633-1-git-send-email-peter.maydell@linaro.org> References: <1333553462-12633-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlUCT3lx0tOpDcyIA0gJKTXtcIkHrkv8dgWMELA7v4xjhmRY28RsYZtk00ynNs2YPS4lo2v Expose the Private Peripheral Interrupt inputs as GPIO inputs. The layout of the GPIO array is thus: [0..N-1] SPIs [N..N+31] PPIs for CPU 0 [N+32..N+63] PPIs for CPU 1 ... Treating PPIs as being another kind of input line is in line with the GIC architecture specification, where they are clearly described that way. The 11MPCore TRM is a bit more ambiguous, but there is no practical difference between "set PPI X as pending" and "0->1 transition on a PPI input line configured as edge triggered", and PPIs are always edge triggered, so this change won't affect behaviour. Signed-off-by: Peter Maydell --- hw/arm_gic.c | 49 ++++++++++++++++++++++++++++++++++++++++--------- 1 files changed, 40 insertions(+), 9 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index df1a34b..fabbcc5 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -192,20 +192,40 @@ gic_set_pending_private(gic_state *s, int cpu, int irq) /* Process a change in an external IRQ input. */ static void gic_set_irq(void *opaque, int irq, int level) { + /* Meaning of the 'irq' parameter: + * [0..N-1] : external interrupts + * [N..N+31] : PPI (internal) interrupts for CPU 0 + * [N+32..N+63] : PPI (internal interrupts for CPU 1 + * ... + */ gic_state *s = (gic_state *)opaque; - /* The first external input line is internal interrupt 32. */ - irq += GIC_INTERNAL; - if (level == GIC_TEST_LEVEL(irq, ALL_CPU_MASK)) + int cm, target; + if (irq < (s->num_irq - GIC_INTERNAL)) { + /* The first external input line is internal interrupt 32. */ + cm = ALL_CPU_MASK; + irq += GIC_INTERNAL; + target = GIC_TARGET(irq); + } else { + int cpu; + irq -= (s->num_irq - GIC_INTERNAL); + cpu = irq / GIC_INTERNAL; + irq %= GIC_INTERNAL; + cm = 1 << cpu; + target = cm; + } + + if (level == GIC_TEST_LEVEL(irq, cm)) { return; + } if (level) { - GIC_SET_LEVEL(irq, ALL_CPU_MASK); - if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, ALL_CPU_MASK)) { - DPRINTF("Set %d pending mask %x\n", irq, GIC_TARGET(irq)); - GIC_SET_PENDING(irq, GIC_TARGET(irq)); + GIC_SET_LEVEL(irq, cm); + if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { + DPRINTF("Set %d pending mask %x\n", irq, target); + GIC_SET_PENDING(irq, target); } } else { - GIC_CLEAR_LEVEL(irq, ALL_CPU_MASK); + GIC_CLEAR_LEVEL(irq, cm); } gic_update(s); } @@ -849,7 +869,18 @@ static void gic_init(gic_state *s, int num_irq) num_irq); } - qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, s->num_irq - GIC_INTERNAL); + i = s->num_irq - GIC_INTERNAL; +#ifndef NVIC + /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. + * GPIO array layout is thus: + * [0..N-1] SPIs + * [N..N+31] PPIs for CPU 0 + * [N+32..N+63] PPIs for CPU 1 + * ... + */ + i += (GIC_INTERNAL * num_cpu); +#endif + qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, i); for (i = 0; i < NUM_CPU(s); i++) { sysbus_init_irq(&s->busdev, &s->parent_irq[i]); }