From patchwork Wed Apr 4 15:30:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7622 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id AE7BC23E5B for ; Wed, 4 Apr 2012 15:31:18 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 76B15A1896F for ; Wed, 4 Apr 2012 15:31:18 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so623238iag.11 for ; Wed, 04 Apr 2012 08:31:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=xkvE05DQp/DIXikjcCJ4hzo0ogDBr/phiLqWAamXOIQ=; b=ME8aQgyWg/lS0uaNmvlkMW8KI6nI/g6l2wl3JLuXFXbSBpz4EMNCkpwdGA6dcCWxMp c8kYFq0op6zpyl8kmZ6iT6YDjGDdRYvhBIis19liROyHXtJesiatFMfPElANUUg2WtSY ZOgYMQ1cx5krLOX6NqL+AhVm9o6N+QiZMWbmwZYqBF4LAhaUhjavpHPAyoZfjYgudCUB zggFTrm8Onj6xBhZrPIoacx3c3LcKaD50XV+7wxgyGbNs3EXbVZ/OlXzYcy+4KbQOUmu ch1m9hvwym+PzS7mfe8ddM3w6TuAWYd6ebNzIKAWq7+WXyeVLjVKddtimNY3q/eGEQdH pPwg== Received: by 10.50.187.225 with SMTP id fv1mr2060240igc.28.1333553478261; Wed, 04 Apr 2012 08:31:18 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.164.217 with SMTP id f25csp45110iby; Wed, 4 Apr 2012 08:31:17 -0700 (PDT) Received: by 10.180.94.161 with SMTP id dd1mr6325874wib.16.1333553476441; Wed, 04 Apr 2012 08:31:16 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id dt4si2569541wib.36.2012.04.04.08.31.15 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 04 Apr 2012 08:31:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SFSAo-0003II-Lh; Wed, 04 Apr 2012 16:31:02 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: Paul Brook , Evgeny Voevodin , patches@linaro.org Subject: [PATCH 02/13] hw/arm_gic: Move gic_get_current_cpu into arm_gic.c Date: Wed, 4 Apr 2012 16:30:51 +0100 Message-Id: <1333553462-12633-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1333553462-12633-1-git-send-email-peter.maydell@linaro.org> References: <1333553462-12633-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlu15FcvUq931lPyvL9Nn/ElzN2UhWA9qJynKChXN7FEmDeBB3FzzviPBUunfDVryLrAEp5 Move the gic_get_current_cpu() function into arm_gic.c. There are only two implementations: (1) "get the index of the currently executing CPU", used by all multicore GICs, and (2) "always 0", used by all GICs instantiated with a single CPU interface (the Realview board GIC and the v7M NVIC). So we can move this into the main GIC source file. Signed-off-by: Peter Maydell Reviewed-by: Evgeny Voevodin --- hw/a15mpcore.c | 8 -------- hw/a9mpcore.c | 9 --------- hw/arm11mpcore.c | 6 ------ hw/arm_gic.c | 20 +++++++++++++++----- hw/armv7m_nvic.c | 7 ------- hw/exynos4210_gic.c | 6 ------ hw/realview_gic.c | 7 ------- 7 files changed, 15 insertions(+), 48 deletions(-) diff --git a/hw/a15mpcore.c b/hw/a15mpcore.c index 67206ec..2e2ed42 100644 --- a/hw/a15mpcore.c +++ b/hw/a15mpcore.c @@ -20,14 +20,6 @@ #include "sysbus.h" -/* Configuration for arm_gic.c: - * how to ID current CPU - */ -static inline int gic_get_current_cpu(void) -{ - return cpu_single_env->cpu_index; -} - #include "arm_gic.c" /* A15MP private memory region. */ diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c index 5bbe3c7..1d83c37 100644 --- a/hw/a9mpcore.c +++ b/hw/a9mpcore.c @@ -10,15 +10,6 @@ #include "sysbus.h" -/* Configuration for arm_gic.c: - * how to ID current CPU - */ -static inline int -gic_get_current_cpu(void) -{ - return cpu_single_env->cpu_index; -} - #include "arm_gic.c" /* A9MP private memory region. */ diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c index 99c1826..c4829d8 100644 --- a/hw/arm11mpcore.c +++ b/hw/arm11mpcore.c @@ -10,12 +10,6 @@ #include "sysbus.h" #include "qemu-timer.h" -static inline int -gic_get_current_cpu(void) -{ - return cpu_single_env->cpu_index; -} - #include "arm_gic.c" /* MPCore private memory region. */ diff --git a/hw/arm_gic.c b/hw/arm_gic.c index f64a001..df1a34b 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -126,6 +126,16 @@ typedef struct gic_state uint32_t num_irq; } gic_state; +static inline int gic_get_current_cpu(gic_state *s) +{ +#if NCPU > 1 + if (s->num_cpu > 1) { + return cpu_single_env->cpu_index; + } +#endif + return 0; +} + /* TODO: Many places that call this routine could be optimized. */ /* Update interrupt status after enabled or pending bits have been changed. */ static void gic_update(gic_state *s) @@ -285,7 +295,7 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) int cm; int mask; - cpu = gic_get_current_cpu(); + cpu = gic_get_current_cpu(s); cm = 1 << cpu; if (offset < 0x100) { #ifndef NVIC @@ -420,7 +430,7 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, int i; int cpu; - cpu = gic_get_current_cpu(); + cpu = gic_get_current_cpu(s); if (offset < 0x100) { #ifdef NVIC goto bad_reg; @@ -582,7 +592,7 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset, int irq; int mask; - cpu = gic_get_current_cpu(); + cpu = gic_get_current_cpu(s); irq = value & 0x3ff; switch ((value >> 24) & 3) { case 0: @@ -665,14 +675,14 @@ static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr, unsigned size) { gic_state *s = (gic_state *)opaque; - return gic_cpu_read(s, gic_get_current_cpu(), addr); + return gic_cpu_read(s, gic_get_current_cpu(s), addr); } static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr, uint64_t value, unsigned size) { gic_state *s = (gic_state *)opaque; - gic_cpu_write(s, gic_get_current_cpu(), addr, value); + gic_cpu_write(s, gic_get_current_cpu(s), addr, value); } /* Wrappers to read/write the GIC CPU interface for a specific CPU. diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index bdab709..99ed85b 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -17,13 +17,6 @@ #define NVIC 1 -/* Only a single "CPU" interface is present. */ -static inline int -gic_get_current_cpu(void) -{ - return 0; -} - static uint32_t nvic_readl(void *opaque, uint32_t offset); static void nvic_writel(void *opaque, uint32_t offset, uint32_t value); diff --git a/hw/exynos4210_gic.c b/hw/exynos4210_gic.c index 426f540..ff7ab84 100644 --- a/hw/exynos4210_gic.c +++ b/hw/exynos4210_gic.c @@ -262,12 +262,6 @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) /********* GIC part *********/ -static inline int -gic_get_current_cpu(void) -{ - return cpu_single_env->cpu_index; -} - #include "arm_gic.c" typedef struct { diff --git a/hw/realview_gic.c b/hw/realview_gic.c index d114242..aa780fe 100644 --- a/hw/realview_gic.c +++ b/hw/realview_gic.c @@ -9,13 +9,6 @@ #include "sysbus.h" -/* Only a single "CPU" interface is present. */ -static inline int -gic_get_current_cpu(void) -{ - return 0; -} - #include "arm_gic.c" typedef struct {