From patchwork Wed Apr 4 15:30:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7628 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id C984623E5B for ; Wed, 4 Apr 2012 15:31:51 +0000 (UTC) Received: from mail-gy0-f180.google.com (mail-gy0-f180.google.com [209.85.160.180]) by fiordland.canonical.com (Postfix) with ESMTP id 828A3A18973 for ; Wed, 4 Apr 2012 15:31:51 +0000 (UTC) Received: by ghbz12 with SMTP id z12so274242ghb.11 for ; Wed, 04 Apr 2012 08:31:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=wMmbDpA9J4+iS3wJ1rLztT3vOpjE4CC86+YLX8ngjI0=; b=oKZ+xHUeyHa9mHTbwFV6zuIq1bo+ydcpS8+ZNOdPA+QNNhp0huwmaQF5PugLz8dvxq 1TxqiqCONO4FoXvb9KRJ6sntc99G0us007Y+4oqPDwW7eE7qKKym6baI1afrKyZNRvLD +OcUY9uT0M6ncy5OQG3O02XcOH0b5HBzZUBUjO53lWZI2dO6AW+9wI/3YfHKZybqVM+y 442/zzA4ViNF8eAuwfWdfdN7boMGv+RcA3hRc1MIWE8TaLhQxhr9awjkXNg4pdY9ZTcR OCeahjxmLTPfpKaRsnHtXmcRGXLHpEEnGsn/Gn8Bnt+hObDZ/Pup0DGt9QZPc1y4Uh4n AHnA== Received: by 10.50.194.232 with SMTP id hz8mr2048962igc.38.1333553510738; Wed, 04 Apr 2012 08:31:50 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.164.217 with SMTP id f25csp45138iby; Wed, 4 Apr 2012 08:31:50 -0700 (PDT) Received: by 10.68.240.135 with SMTP id wa7mr38237710pbc.7.1333553509912; Wed, 04 Apr 2012 08:31:49 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id d3si1322511pbh.27.2012.04.04.08.31.49 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 04 Apr 2012 08:31:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SFSAo-0003IG-Id; Wed, 04 Apr 2012 16:31:02 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: Paul Brook , Evgeny Voevodin , patches@linaro.org Subject: [PATCH 01/13] hw/arm_gic: Move NCPU definition to arm_gic.c Date: Wed, 4 Apr 2012 16:30:50 +0100 Message-Id: <1333553462-12633-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1333553462-12633-1-git-send-email-peter.maydell@linaro.org> References: <1333553462-12633-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQkwAi4GnnGJ0qM0w3GMvmG4oskZJ68h1KeNb5mtLImVDYQ8tshdB/K5kGmreVxrLE2X2Pln Move the NCPU definition to arm_gic.c: the maximum number of CPU interfaces is defined by the GIC architecture specification to be 8, so we don't need to have this #define in each of the sources files which currently includes arm_gic.c. Signed-off-by: Peter Maydell Reviewed-by: Evgeny Voevodin --- hw/a15mpcore.c | 8 +------- hw/a9mpcore.c | 8 +------- hw/arm11mpcore.c | 2 -- hw/arm_gic.c | 13 ++++++++++++- hw/armv7m_nvic.c | 1 - hw/exynos4210_gic.c | 9 ++++----- hw/realview_gic.c | 4 +--- 7 files changed, 19 insertions(+), 26 deletions(-) diff --git a/hw/a15mpcore.c b/hw/a15mpcore.c index 71142e5..67206ec 100644 --- a/hw/a15mpcore.c +++ b/hw/a15mpcore.c @@ -21,10 +21,8 @@ #include "sysbus.h" /* Configuration for arm_gic.c: - * max number of CPUs, how to ID current CPU + * how to ID current CPU */ -#define NCPU 4 - static inline int gic_get_current_cpu(void) { return cpu_single_env->cpu_index; @@ -45,10 +43,6 @@ static int a15mp_priv_init(SysBusDevice *dev) { A15MPPrivState *s = FROM_SYSBUSGIC(A15MPPrivState, dev); - if (s->num_cpu > NCPU) { - hw_error("a15mp_priv_init: num-cpu may not be more than %d\n", NCPU); - } - gic_init(&s->gic, s->num_cpu, s->num_irq); /* Memory map (addresses are offsets from PERIPHBASE): diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c index 03b128c..5bbe3c7 100644 --- a/hw/a9mpcore.c +++ b/hw/a9mpcore.c @@ -11,10 +11,8 @@ #include "sysbus.h" /* Configuration for arm_gic.c: - * max number of CPUs, how to ID current CPU + * how to ID current CPU */ -#define NCPU 4 - static inline int gic_get_current_cpu(void) { @@ -149,10 +147,6 @@ static int a9mp_priv_init(SysBusDevice *dev) SysBusDevice *busdev; int i; - if (s->num_cpu > NCPU) { - hw_error("a9mp_priv_init: num-cpu may not be more than %d\n", NCPU); - } - gic_init(&s->gic, s->num_cpu, s->num_irq); s->mptimer = qdev_create(NULL, "arm_mptimer"); diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c index ba6a89d..99c1826 100644 --- a/hw/arm11mpcore.c +++ b/hw/arm11mpcore.c @@ -10,8 +10,6 @@ #include "sysbus.h" #include "qemu-timer.h" -#define NCPU 4 - static inline int gic_get_current_cpu(void) { diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 6b34c06..f64a001 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -15,6 +15,13 @@ #define GIC_MAXIRQ 1020 /* First 32 are private to each CPU (SGIs and PPIs). */ #define GIC_INTERNAL 32 +/* Maximum number of possible CPU interfaces, determined by GIC architecture */ +#ifdef NVIC +#define NCPU 1 +#else +#define NCPU 8 +#endif + //#define DEBUG_GIC #ifdef DEBUG_GIC @@ -50,7 +57,7 @@ typedef struct gic_irq_state unsigned trigger:1; /* nonzero = edge triggered. */ } gic_irq_state; -#define ALL_CPU_MASK ((1 << NCPU) - 1) +#define ALL_CPU_MASK ((unsigned)(((1 << NCPU) - 1))) #if NCPU > 1 #define NUM_CPU(s) ((s)->num_cpu) #else @@ -813,6 +820,10 @@ static void gic_init(gic_state *s, int num_irq) #if NCPU > 1 s->num_cpu = num_cpu; + if (s->num_cpu > NCPU) { + hw_error("requested %u CPUs exceeds GIC maximum %d\n", + num_cpu, NCPU); + } #endif s->num_irq = num_irq + GIC_BASE_IRQ; if (s->num_irq > GIC_MAXIRQ) { diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index 3210129..bdab709 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -15,7 +15,6 @@ #include "arm-misc.h" #include "exec-memory.h" -#define NCPU 1 #define NVIC 1 /* Only a single "CPU" interface is present. */ diff --git a/hw/exynos4210_gic.c b/hw/exynos4210_gic.c index 3ba9063..426f540 100644 --- a/hw/exynos4210_gic.c +++ b/hw/exynos4210_gic.c @@ -174,7 +174,6 @@ combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { }; #define EXYNOS4210_GIC_NIRQ 160 -#define NCPU EXYNOS4210_NCPUS #define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000 #define EXYNOS4210_EXT_GIC_DIST_REGION_SIZE 0x10000 @@ -275,8 +274,8 @@ typedef struct { gic_state gic; MemoryRegion cpu_container; MemoryRegion dist_container; - MemoryRegion cpu_alias[NCPU]; - MemoryRegion dist_alias[NCPU]; + MemoryRegion cpu_alias[EXYNOS4210_NCPUS]; + MemoryRegion dist_alias[EXYNOS4210_NCPUS]; uint32_t num_cpu; } Exynos4210GicState; @@ -359,7 +358,7 @@ type_init(exynos4210_gic_register_types) typedef struct { SysBusDevice busdev; - qemu_irq pic_irq[NCPU]; /* output IRQs to PICs */ + qemu_irq pic_irq[EXYNOS4210_NCPUS]; /* output IRQs to PICs */ uint32_t gpio_level[EXYNOS4210_IRQ_GATE_NINPUTS]; /* Input levels */ } Exynos4210IRQGateState; @@ -424,7 +423,7 @@ static int exynos4210_irq_gate_init(SysBusDevice *dev) EXYNOS4210_IRQ_GATE_NINPUTS); /* Connect SysBusDev irqs to device specific irqs */ - for (i = 0; i < NCPU; i++) { + for (i = 0; i < EXYNOS4210_NCPUS; i++) { sysbus_init_irq(dev, &s->pic_irq[i]); } diff --git a/hw/realview_gic.c b/hw/realview_gic.c index 071ef13..d114242 100644 --- a/hw/realview_gic.c +++ b/hw/realview_gic.c @@ -9,8 +9,6 @@ #include "sysbus.h" -#define NCPU 1 - /* Only a single "CPU" interface is present. */ static inline int gic_get_current_cpu(void) @@ -40,7 +38,7 @@ static int realview_gic_init(SysBusDevice *dev) * number of interrupt lines, so we don't need to expose this as * a qdev property. */ - gic_init(&s->gic, 96); + gic_init(&s->gic, 1, 96); realview_gic_map_setup(s); sysbus_init_mmio(dev, &s->container); return 0;