From patchwork Fri Mar 30 13:00:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7544 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 71DE223E29 for ; Fri, 30 Mar 2012 13:26:40 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 38E8CA185B4 for ; Fri, 30 Mar 2012 13:26:40 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so1366999iag.11 for ; Fri, 30 Mar 2012 06:26:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-forwarded-to:x-forwarded-for:delivered-to :received-spf:from:to:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=3ATfPHcrk1JE4gorGYX+FHBLuCKHP0yS2wGPPrZ8sMA=; b=gtfW80TVo7iWFTv0XdwG7OxE9vXtSVyeBOBOgYQXkpeeSiTcV3sU0m3JHweUw5hH7z punDCxj4D6q5SKdqeN/Z8m+L1Zng50RAsoiJVZ9MeRVIiv3lQI/R0tW2KTyv2qK7rbY2 tB9FwGJ7LV92gpQzf5tg1FwPWolwDsCqRp66MD/ddRw9ZM9za7nF6CIvMDoMDfxHksFr zRZS5fxTbW/Ok938AyhnFoA5gOP/xZ7wUSZEV6OLkr06CFJu0HCAFrxeNCOI4/9N0Zz4 rTznJeaZkFBEmEkoMfNY1PXXiAQA5910R9Jtf5tSv7iABTHVqrVa+E8oAdGkglNGESHP mhPg== MIME-Version: 1.0 Received: by 10.50.191.233 with SMTP id hb9mr1315371igc.44.1333113999978; Fri, 30 Mar 2012 06:26:39 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.5.205 with SMTP id 13csp22416ibw; Fri, 30 Mar 2012 06:26:39 -0700 (PDT) Received: by 10.180.107.104 with SMTP id hb8mr6492922wib.8.1333113997830; Fri, 30 Mar 2012 06:26:37 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id f10si2601195wif.8.2012.03.30.06.26.37 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 30 Mar 2012 06:26:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SDbRb-00011F-KQ for patches@linaro.org; Fri, 30 Mar 2012 14:00:43 +0100 From: Peter Maydell To: patches@linaro.org Subject: [PATCH 08/14] target-arm: Move iWMMXT wCID reset to cpu_state_reset Date: Fri, 30 Mar 2012 14:00:36 +0100 Message-Id: <1333112442-3871-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1333112442-3871-1-git-send-email-peter.maydell@linaro.org> References: <1333112442-3871-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQk87qEaKg1icmZIlwUWS2gCUA2A51LwM+o6HqQwnwBnWMKab0RdXxV2scyCq5x5MUtEV/WP Move the iWMMXT wCID reset to cpu_state_reset(). Since we use the same value for all CPUs with this feature (with the major/minor revision fields set to the QEMU specific 'Q' value) there's no need to create an ARMCPU field just for this. Signed-off-by: Peter Maydell --- target-arm/helper.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index e3e019a..0bc5529 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -122,7 +122,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA270_B1: case ARM_CPUID_PXA270_C0: case ARM_CPUID_PXA270_C5: - env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; break; case ARM_CPUID_SA1100: case ARM_CPUID_SA1110: @@ -162,6 +161,10 @@ void cpu_state_reset(CPUARMState *env) env->cp15.c0_cachetype = cpu->ctr; env->cp15.c1_sys = cpu->reset_sctlr; + if (arm_feature(env, ARM_FEATURE_IWMMXT)) { + env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; + } + #if defined (CONFIG_USER_ONLY) env->uncached_cpsr = ARM_CPU_MODE_USR; /* For user mode we must enable access to coprocessors */