From patchwork Fri Mar 30 13:00:34 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7537 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 17A8523E13 for ; Fri, 30 Mar 2012 13:00:51 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id C5973A18709 for ; Fri, 30 Mar 2012 13:00:50 +0000 (UTC) Received: by yhpp61 with SMTP id p61so293558yhp.11 for ; Fri, 30 Mar 2012 06:00:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-forwarded-to:x-forwarded-for:delivered-to :received-spf:from:to:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=JYkKHxOE5xMlcnwjVZ16miYaJWoP+eG3VUP6ba3bBGs=; b=l6rdplYI/Do3KEUtJ9xM5mVQvJ5Lx/j+g13rKGieseb4hRiWfiF9L3d3S9QaIr4RZD fBABGyjbBQj4kvTAaHR4b/dVeO+NOEig2BwumueV1XCLYhSYqWhM2kSjIjbOR7aIL5iJ Ki175gMoJdkwAjXHQgG3u6NuaOE/mLRy9RTJj+LQhvVXIZ5JuHH369GkfrsaCD9kGDYf Yj9Kr9DFoci1RIB/GNnCtprb+Gjqa/xWKIquM4FZMjkj97BkWmF20LNGhNtTUUxuY6Pp VXlpuHuUrAHUBR86TT+Bt1Ekitk6QxhOVy7o3y63hRlGIeZuXupuU6L+qb3Be8BIygHv rALg== MIME-Version: 1.0 Received: by 10.50.46.195 with SMTP id x3mr1263807igm.54.1333112450088; Fri, 30 Mar 2012 06:00:50 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.5.205 with SMTP id 13csp21191ibw; Fri, 30 Mar 2012 06:00:48 -0700 (PDT) Received: by 10.236.136.198 with SMTP id w46mr512614yhi.68.1333112446688; Fri, 30 Mar 2012 06:00:46 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id z6si4290566ane.209.2012.03.30.06.00.45 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 30 Mar 2012 06:00:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SDbRb-00011B-Fx for patches@linaro.org; Fri, 30 Mar 2012 14:00:43 +0100 From: Peter Maydell To: patches@linaro.org Subject: [PATCH 06/14] target-arm: Move SCTLR reset value setup to per cpu init fns Date: Fri, 30 Mar 2012 14:00:34 +0100 Message-Id: <1333112442-3871-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1333112442-3871-1-git-send-email-peter.maydell@linaro.org> References: <1333112442-3871-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQkERH9O4I7cKBxxYahJzcJAnHe6Eupx6qWk/ONq98x3CNeqOw4ULnf8Ag1+m/gusoGepgnd Move the reset value of SCTLR to ARMCPU, initialised in the per-cpu init functions. It can then be reset by a simple copy, and we can drop the code from cpu_reset_model_id(). Signed-off-by: Peter Maydell --- target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 23 +++++++++++++++++++++++ target-arm/helper.c | 13 +------------ 3 files changed, 25 insertions(+), 12 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index fc147c4..5e7a558 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -67,6 +67,7 @@ typedef struct ARMCPU { uint32_t mvfr0; uint32_t mvfr1; uint32_t ctr; + uint32_t reset_sctlr; } ARMCPU; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 115561c..c33a451 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -105,6 +105,7 @@ static void arm926_initfn(Object *obj) cpu->midr = ARM_CPUID_ARM926; cpu->reset_fpsid = 0x41011090; cpu->ctr = 0x1dd20d2; + cpu->reset_sctlr = 0x00090078; arm_cpu_postconfig_init(cpu); } @@ -115,6 +116,7 @@ static void arm946_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_MPU); cpu->midr = ARM_CPUID_ARM946; cpu->ctr = 0x0f004006; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -127,6 +129,7 @@ static void arm1026_initfn(Object *obj) cpu->midr = ARM_CPUID_ARM1026; cpu->reset_fpsid = 0x410110a0; cpu->ctr = 0x1dd20d2; + cpu->reset_sctlr = 0x00090078; arm_cpu_postconfig_init(cpu); } @@ -140,6 +143,7 @@ static void arm1136_r2_initfn(Object *obj) cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; cpu->ctr = 0x1dd20d2; + cpu->reset_sctlr = 0x00050078; arm_cpu_postconfig_init(cpu); } @@ -154,6 +158,7 @@ static void arm1136_initfn(Object *obj) cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; cpu->ctr = 0x1dd20d2; + cpu->reset_sctlr = 0x00050078; arm_cpu_postconfig_init(cpu); } @@ -168,6 +173,7 @@ static void arm1176_initfn(Object *obj) cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; cpu->ctr = 0x1dd20d2; + cpu->reset_sctlr = 0x00050078; arm_cpu_postconfig_init(cpu); } @@ -206,6 +212,7 @@ static void cortex_a8_initfn(Object *obj) cpu->mvfr0 = 0x11110222; cpu->mvfr1 = 0x00011100; cpu->ctr = 0x82048004; + cpu->reset_sctlr = 0x00c50078; arm_cpu_postconfig_init(cpu); } @@ -227,6 +234,7 @@ static void cortex_a9_initfn(Object *obj) cpu->mvfr0 = 0x11110222; cpu->mvfr1 = 0x01111111; cpu->ctr = 0x80038003; + cpu->reset_sctlr = 0x00c50078; arm_cpu_postconfig_init(cpu); } @@ -246,6 +254,7 @@ static void cortex_a15_initfn(Object *obj) cpu->mvfr0 = 0x10110222; cpu->mvfr1 = 0x11111111; cpu->ctr = 0x8444c004; + cpu->reset_sctlr = 0x00c50078; arm_cpu_postconfig_init(cpu); } @@ -256,6 +265,7 @@ static void ti925t_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_OMAPCP); cpu->midr = ARM_CPUID_TI925T; cpu->ctr = 0x5109149; + cpu->reset_sctlr = 0x00000070; arm_cpu_postconfig_init(cpu); } @@ -264,6 +274,7 @@ static void sa1100_initfn(Object *obj) ARMCPU *cpu = ARM_CPU(obj); set_feature(&cpu->env, ARM_FEATURE_STRONGARM); cpu->midr = ARM_CPUID_SA1100; + cpu->reset_sctlr = 0x00000070; arm_cpu_postconfig_init(cpu); } @@ -272,6 +283,7 @@ static void sa1110_initfn(Object *obj) ARMCPU *cpu = ARM_CPU(obj); set_feature(&cpu->env, ARM_FEATURE_STRONGARM); cpu->midr = ARM_CPUID_SA1110; + cpu->reset_sctlr = 0x00000070; arm_cpu_postconfig_init(cpu); } @@ -282,6 +294,7 @@ static void pxa250_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA250; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -292,6 +305,7 @@ static void pxa255_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA255; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -302,6 +316,7 @@ static void pxa260_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA260; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -312,6 +327,7 @@ static void pxa261_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA261; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -322,6 +338,7 @@ static void pxa262_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->midr = ARM_CPUID_PXA262; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -333,6 +350,7 @@ static void pxa270a0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_A0; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -344,6 +362,7 @@ static void pxa270a1_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_A1; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -355,6 +374,7 @@ static void pxa270b0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_B0; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -366,6 +386,7 @@ static void pxa270b1_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_B1; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -377,6 +398,7 @@ static void pxa270c0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->midr = ARM_CPUID_PXA270_C0; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -392,6 +414,7 @@ static void pxa270c5_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7MP); cpu->midr = ARM_CPUID_PXA270_C5; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } diff --git a/target-arm/helper.c b/target-arm/helper.c index e1314c2..cb0ae15 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -51,13 +51,10 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) { switch (id) { case ARM_CPUID_ARM926: - env->cp15.c1_sys = 0x00090078; break; case ARM_CPUID_ARM946: - env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_ARM1026: - env->cp15.c1_sys = 0x00090078; break; case ARM_CPUID_ARM1136: /* This is the 1136 r1, which is a v6K core */ @@ -72,12 +69,10 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) */ memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM1176: memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM11MPCORE: memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -90,7 +85,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */ env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */ env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */ - env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA9: memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -98,7 +92,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3; env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */ env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */ - env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA15: memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -107,7 +100,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */ env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */ env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */ - env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXM3: break; @@ -115,7 +107,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_TI915T: case ARM_CPUID_TI925T: - env->cp15.c1_sys = 0x00000070; env->cp15.c15_i_max = 0x000; env->cp15.c15_i_min = 0xff0; break; @@ -125,7 +116,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA261: case ARM_CPUID_PXA262: /* JTAG_ID is ((id << 28) | 0x09265013) */ - env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_PXA270_A0: case ARM_CPUID_PXA270_A1: @@ -135,11 +125,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA270_C5: /* JTAG_ID is ((id << 28) | 0x09265013) */ env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; - env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_SA1100: case ARM_CPUID_SA1110: - env->cp15.c1_sys = 0x00000070; break; default: cpu_abort(env, "Bad CPU ID: %x\n", id); @@ -174,6 +162,7 @@ void cpu_state_reset(CPUARMState *env) env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; env->cp15.c0_cachetype = cpu->ctr; + env->cp15.c1_sys = cpu->reset_sctlr; #if defined (CONFIG_USER_ONLY) env->uncached_cpsr = ARM_CPU_MODE_USR;