From patchwork Fri Mar 30 13:00:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7540 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 6482E23E29 for ; Fri, 30 Mar 2012 13:26:35 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 0F749A18710 for ; Fri, 30 Mar 2012 13:26:34 +0000 (UTC) Received: by iage36 with SMTP id e36so1366999iag.11 for ; Fri, 30 Mar 2012 06:26:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-forwarded-to:x-forwarded-for:delivered-to :received-spf:from:to:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=5pCIzpoe+jUlgvx2DM7HVRC/5VpsXqUTYs1haRvIvvs=; b=PHvG9otJksDXbjgzcM02evbbLNzWAiojV5vIdphaM9YA8Ce0Kkce/Vy4VqaDeVvEaq 7Tu2W0KarysKNteGCECR5c2JgcKxbvcKCx/uaqcNW0SGDeR5mDATHvHm8My7mQmcAxN4 k/sy4nakjCzF5nKZxR0wZLHunXS/2FUjLerKNQlCtM/EVweTkTMrJfSxessX+5Ndjh1u oq5zlLK5dJd8DKx/LfWw7Wnv1CAkegtpSKk0Z1tz1U+haAMyI8sgHYzRq2DGm4KzsOcN XbEU3nzVJDAOlqu1lddBR32zlbjJN38REWM8XP0fjRrAcqSBSllZ8oieo4t0E9dC7RVQ YAzA== MIME-Version: 1.0 Received: by 10.50.46.164 with SMTP id w4mr1393579igm.54.1333113994454; Fri, 30 Mar 2012 06:26:34 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.5.205 with SMTP id 13csp22404ibw; Fri, 30 Mar 2012 06:26:33 -0700 (PDT) Received: by 10.180.102.100 with SMTP id fn4mr6578468wib.1.1333113992041; Fri, 30 Mar 2012 06:26:32 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id h2si5940586wiz.2.2012.03.30.06.26.31 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 30 Mar 2012 06:26:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SDbRc-00011a-2O for patches@linaro.org; Fri, 30 Mar 2012 14:00:44 +0100 From: Peter Maydell To: patches@linaro.org Subject: [PATCH 14/14] target-arm: Move A9 config_base_address reset value to ARMCPU Date: Fri, 30 Mar 2012 14:00:42 +0100 Message-Id: <1333112442-3871-15-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1333112442-3871-1-git-send-email-peter.maydell@linaro.org> References: <1333112442-3871-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQkdR+nj4L6sqMW04lOwRd/Flm3deup2J1/PnzL6IgB6n10TVWLxWWzZhm918z4XF9CA0vPu Move the A9 config_base_address cp15 register reset value to ARMCPU. This should become a QOM property so that the Highbank board can set it without having to pull in cpu-qom.h, but at least this avoids the implicit dependency on reset ordering that the previous workaround had. Cc: Mark Langsdorf Signed-off-by: Peter Maydell --- hw/highbank.c | 12 +++++------- target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 4 +--- 3 files changed, 7 insertions(+), 10 deletions(-) diff --git a/hw/highbank.c b/hw/highbank.c index 906eed5..b007f97 100644 --- a/hw/highbank.c +++ b/hw/highbank.c @@ -27,6 +27,7 @@ #include "sysbus.h" #include "blockdev.h" #include "exec-memory.h" +#include "cpu-qom.h" #define SMP_BOOT_ADDR 0x100 #define SMP_BOOT_REG 0x40 @@ -35,12 +36,6 @@ #define NIRQ_GIC 160 /* Board init. */ -static void highbank_cpu_reset(void *opaque) -{ - CPUARMState *env = opaque; - - env->cp15.c15_config_base_address = GIC_BASE_ADDR; -} static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info) { @@ -213,14 +208,17 @@ static void highbank_init(ram_addr_t ram_size, } for (n = 0; n < smp_cpus; n++) { + ARMCPU *cpu; env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } + cpu = arm_env_get_cpu(env); + /* This will become a QOM property eventually */ + cpu->reset_cbar = GIC_BASE_ADDR; irqp = arm_pic_init_cpu(env); cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; - qemu_register_reset(highbank_cpu_reset, env); } sysmem = get_system_memory(); diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 55dc920..c42755a 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -84,6 +84,7 @@ typedef struct ARMCPU { uint32_t id_isar5; uint32_t clidr; uint32_t ccsidr[16]; + uint32_t reset_cbar; } ARMCPU; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 66f76a8..653e2b3 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -30,7 +30,6 @@ static void arm_cpu_reset(CPUState *s) ARMCPU *cpu = ARM_CPU(s); ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); CPUARMState *env = &cpu->env; - uint32_t tmp = 0; if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); @@ -39,9 +38,8 @@ static void arm_cpu_reset(CPUState *s) acc->parent_reset(s); - tmp = env->cp15.c15_config_base_address; memset(env, 0, offsetof(CPUARMState, breakpoints)); - env->cp15.c15_config_base_address = tmp; + env->cp15.c15_config_base_address = cpu->reset_cbar; env->cp15.c0_cpuid = cpu->midr; env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;