From patchwork Fri Mar 30 13:00:40 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7541 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 9B68823E29 for ; Fri, 30 Mar 2012 13:26:37 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 61E89A18711 for ; Fri, 30 Mar 2012 13:26:37 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so1366999iag.11 for ; Fri, 30 Mar 2012 06:26:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-forwarded-to:x-forwarded-for:delivered-to :received-spf:from:to:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=Nb13lPmbZrBtU5PtbvEdy0m5Aq2j/h8MLu1nW0Mdpt0=; b=Gm9mljWYBRZwcpKkb6p+XLG5qztNj5EIeD55ZwV75Z/mKd+xfrA/rmPkLu6qkPBfGI 0uz4YnZFGg8nWvjhFDXRVA55wsMz449xd2AXXDJrKIgOcx96U0IWhunFhF5Kk+ghtBOW P9hWEo/KukxaOfhMjmP5DuiVJ222vtJ42EhOJu6b/3Z3J+VNDNP3LbYCxdjkjNv3TqlD PL7flmE5XU4h2KCwo3H2hwdRLmUkHTOQwiYr1k/IsEH0hyW3U/q6amFQ381ZYFU6Eh55 4tJer0s82oRWhBccaReYBa02+MUC8RnZzLkFmyPG1y7dt6E+hLEMHniHEUlePs9E4fGh ngrg== MIME-Version: 1.0 Received: by 10.50.45.234 with SMTP id q10mr1340085igm.54.1333113997142; Fri, 30 Mar 2012 06:26:37 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.5.205 with SMTP id 13csp22409ibw; Fri, 30 Mar 2012 06:26:36 -0700 (PDT) Received: by 10.180.81.37 with SMTP id w5mr6458934wix.16.1333113994976; Fri, 30 Mar 2012 06:26:34 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id l6si2609323wic.12.2012.03.30.06.26.34 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 30 Mar 2012 06:26:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SDbRb-00011U-UK for patches@linaro.org; Fri, 30 Mar 2012 14:00:43 +0100 From: Peter Maydell To: patches@linaro.org Subject: [PATCH 12/14] target-arm: Drop cpu_reset_model_id() Date: Fri, 30 Mar 2012 14:00:40 +0100 Message-Id: <1333112442-3871-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1333112442-3871-1-git-send-email-peter.maydell@linaro.org> References: <1333112442-3871-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQm9ULQ0wuXu8xc9hFPXOUM69e/jK0/QgPNQczgu+47lDf1EucKrxOTePkdFg1MgqUHSs7qH cpu_reset_model_id() is now empty and we can remove it. Signed-off-by: Peter Maydell --- target-arm/helper.c | 59 +-------------------------------------------------- 1 files changed, 1 insertions(+), 58 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 5c4cfee..f48108e 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -8,66 +8,12 @@ #include "sysemu.h" #include "cpu-qom.h" -static void cpu_reset_model_id(CPUARMState *env, uint32_t id) -{ - switch (id) { - case ARM_CPUID_ARM926: - break; - case ARM_CPUID_ARM946: - break; - case ARM_CPUID_ARM1026: - break; - case ARM_CPUID_ARM1136: - /* This is the 1136 r1, which is a v6K core */ - case ARM_CPUID_ARM1136_R2: - break; - case ARM_CPUID_ARM1176: - break; - case ARM_CPUID_ARM11MPCORE: - break; - case ARM_CPUID_CORTEXA8: - break; - case ARM_CPUID_CORTEXA9: - break; - case ARM_CPUID_CORTEXA15: - break; - case ARM_CPUID_CORTEXM3: - break; - case ARM_CPUID_ANY: /* For userspace emulation. */ - break; - case ARM_CPUID_TI915T: - case ARM_CPUID_TI925T: - break; - case ARM_CPUID_PXA250: - case ARM_CPUID_PXA255: - case ARM_CPUID_PXA260: - case ARM_CPUID_PXA261: - case ARM_CPUID_PXA262: - break; - case ARM_CPUID_PXA270_A0: - case ARM_CPUID_PXA270_A1: - case ARM_CPUID_PXA270_B0: - case ARM_CPUID_PXA270_B1: - case ARM_CPUID_PXA270_C0: - case ARM_CPUID_PXA270_C5: - break; - case ARM_CPUID_SA1100: - case ARM_CPUID_SA1110: - break; - default: - cpu_abort(env, "Bad CPU ID: %x\n", id); - break; - } - -} - /* TODO Move contents into arm_cpu_reset() in cpu.c, * once cpu_reset_model_id() is eliminated, * and then forward to cpu_reset() here. */ void cpu_state_reset(CPUARMState *env) { - uint32_t id; uint32_t tmp = 0; ARMCPU *cpu = arm_env_get_cpu(env); @@ -76,11 +22,8 @@ void cpu_state_reset(CPUARMState *env) log_cpu_state(env, 0); } - id = env->cp15.c0_cpuid; tmp = env->cp15.c15_config_base_address; memset(env, 0, offsetof(CPUARMState, breakpoints)); - if (id) - cpu_reset_model_id(env, id); env->cp15.c15_config_base_address = tmp; env->cp15.c0_cpuid = cpu->midr; env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; @@ -145,7 +88,7 @@ void cpu_state_reset(CPUARMState *env) /* v7 performance monitor control register: same implementor * field as main ID register, and we implement no event counters. */ - env->cp15.c9_pmcr = (id & 0xff000000); + env->cp15.c9_pmcr = (cpu->midr & 0xff000000); #endif set_flush_to_zero(1, &env->vfp.standard_fp_status); set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);