From patchwork Fri Mar 30 13:00:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7547 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 45DA023E29 for ; Fri, 30 Mar 2012 13:26:44 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id 1675CA185B4 for ; Fri, 30 Mar 2012 13:26:44 +0000 (UTC) Received: by mail-yw0-f52.google.com with SMTP id p61so320221yhp.11 for ; Fri, 30 Mar 2012 06:26:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-forwarded-to:x-forwarded-for:delivered-to :received-spf:from:to:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=2ztCvObwwpp+foRc2RatIBzkjMbg6IbQeo9g3bD13pg=; b=XzvWTEjJ7rOdaAyLqXh5E5EBvEjsIKnpFU/ZBb7bu8FCUPw4ghKmwIK+FDhb9F9Ip+ edrmmSCCgfrMtHGfz6N27AFN29B4jTDu3h1btk68H/5pTfzdQcoM687N9r/PQxzHfVjF f8D6uJphdKebkapPTer1TY05UZDMPMPBWDOauMOuhoQ1q2iiEx3z4NsvJG6ongYKygbZ Rz0eUax/otlEPX5DAf4FMJH605pTwOKvRMR7laxGY11s0NLz9UHpObb0bLv51Vg/xaeq hL0I8Xk2Jt2dNbf62LaxsPoOUPKsutq8tLPTU6T15zIKvbG9+Cx+OA04d5xNnmYRiWYA mPUA== MIME-Version: 1.0 Received: by 10.50.194.226 with SMTP id hz2mr1365918igc.44.1333114003792; Fri, 30 Mar 2012 06:26:43 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.5.205 with SMTP id 13csp22426ibw; Fri, 30 Mar 2012 06:26:43 -0700 (PDT) Received: by 10.180.91.10 with SMTP id ca10mr6453780wib.17.1333114001930; Fri, 30 Mar 2012 06:26:41 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id y6si2605142wix.16.2012.03.30.06.26.41 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 30 Mar 2012 06:26:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SDbRb-00011J-P0 for patches@linaro.org; Fri, 30 Mar 2012 14:00:43 +0100 From: Peter Maydell To: patches@linaro.org Subject: [PATCH 10/14] target-arm: Move OMAP cp15_i_{max, min} reset to cpu_state_reset Date: Fri, 30 Mar 2012 14:00:38 +0100 Message-Id: <1333112442-3871-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1333112442-3871-1-git-send-email-peter.maydell@linaro.org> References: <1333112442-3871-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQnZv5SndmrJ+aCJk/raSBn9MSfvygowuQYN18tl7bu8W+LUWkhhkzpLFtgfNp6praO9SQKI Move the OMAP-specific cp15_i_{max,min} reset to cpu_state_reset; since these registers are only accessible on CPUs with the OMAPCP feature set there's no need to guard this reset with either a CPUID or feature bit check. Signed-off-by: Peter Maydell --- target-arm/helper.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 6c21f74..a94f09f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -48,8 +48,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_TI915T: case ARM_CPUID_TI925T: - env->cp15.c15_i_max = 0x000; - env->cp15.c15_i_min = 0xff0; break; case ARM_CPUID_PXA250: case ARM_CPUID_PXA255: @@ -115,6 +113,7 @@ void cpu_state_reset(CPUARMState *env) env->cp15.c0_c2[3] = cpu->id_isar3; env->cp15.c0_c2[4] = cpu->id_isar4; env->cp15.c0_c2[5] = cpu->id_isar5; + env->cp15.c15_i_min = 0xff0; if (arm_feature(env, ARM_FEATURE_IWMMXT)) { env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';