From patchwork Thu Mar 8 13:56:26 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7170 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 062DF23E01 for ; Thu, 8 Mar 2012 13:56:32 +0000 (UTC) Received: from mail-gy0-f180.google.com (mail-gy0-f180.google.com [209.85.160.180]) by fiordland.canonical.com (Postfix) with ESMTP id BF4D8A185EC for ; Thu, 8 Mar 2012 13:56:31 +0000 (UTC) Received: by ghbz12 with SMTP id z12so207928ghb.11 for ; Thu, 08 Mar 2012 05:56:31 -0800 (PST) Received: by 10.50.183.137 with SMTP id em9mr8873374igc.58.1331214991043; Thu, 08 Mar 2012 05:56:31 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.53.18 with SMTP id k18csp10033ibg; Thu, 8 Mar 2012 05:56:29 -0800 (PST) Received: by 10.216.134.136 with SMTP id s8mr3399267wei.6.1331214989067; Thu, 08 Mar 2012 05:56:29 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id ex3si2742288wib.5.2012.03.08.05.56.28 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 08 Mar 2012 05:56:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1S5dpS-0007UD-NU; Thu, 08 Mar 2012 13:56:26 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH] ARM: Remove unnecessary subpage workarounds Date: Thu, 8 Mar 2012 13:56:26 +0000 Message-Id: <1331214986-28754-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 X-Gm-Message-State: ALoCoQko+Scc5mUmThvUccei6l7wAVlFbNdhl8yPi4EwE2w+MqpBO/uP5T3/YicmBhKexj4TGtqf In the ARM per-CPU peripherals (GIC, private timers, SCU, etc), remove workarounds for subpage memory region read/write functions being passed offsets from the start of the page rather than the start of the region. Following commit 5312bd8b3 the masking off of high bits of the address offset is now harmless but unnecessary. Signed-off-by: Peter Maydell Reviewed-by: Andreas Färber --- hw/arm11mpcore.c | 2 -- hw/arm_gic.c | 8 ++++---- hw/arm_mptimer.c | 2 -- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c index c67b70f..ba6a89d 100644 --- a/hw/arm11mpcore.c +++ b/hw/arm11mpcore.c @@ -42,7 +42,6 @@ static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset, { mpcore_priv_state *s = (mpcore_priv_state *)opaque; int id; - offset &= 0xff; /* SCU */ switch (offset) { case 0x00: /* Control. */ @@ -63,7 +62,6 @@ static void mpcore_scu_write(void *opaque, target_phys_addr_t offset, uint64_t value, unsigned size) { mpcore_priv_state *s = (mpcore_priv_state *)opaque; - offset &= 0xff; /* SCU */ switch (offset) { case 0: /* Control register. */ diff --git a/hw/arm_gic.c b/hw/arm_gic.c index d8a7a19..6b34c06 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -658,14 +658,14 @@ static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr, unsigned size) { gic_state *s = (gic_state *)opaque; - return gic_cpu_read(s, gic_get_current_cpu(), addr & 0xff); + return gic_cpu_read(s, gic_get_current_cpu(), addr); } static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr, uint64_t value, unsigned size) { gic_state *s = (gic_state *)opaque; - gic_cpu_write(s, gic_get_current_cpu(), addr & 0xff, value); + gic_cpu_write(s, gic_get_current_cpu(), addr, value); } /* Wrappers to read/write the GIC CPU interface for a specific CPU. @@ -677,7 +677,7 @@ static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr, gic_state **backref = (gic_state **)opaque; gic_state *s = *backref; int id = (backref - s->backref); - return gic_cpu_read(s, id, addr & 0xff); + return gic_cpu_read(s, id, addr); } static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr, @@ -686,7 +686,7 @@ static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr, gic_state **backref = (gic_state **)opaque; gic_state *s = *backref; int id = (backref - s->backref); - gic_cpu_write(s, id, addr & 0xff, value); + gic_cpu_write(s, id, addr, value); } static const MemoryRegionOps gic_thiscpu_ops = { diff --git a/hw/arm_mptimer.c b/hw/arm_mptimer.c index 361e887..df7fb4c 100644 --- a/hw/arm_mptimer.c +++ b/hw/arm_mptimer.c @@ -97,7 +97,6 @@ static uint64_t timerblock_read(void *opaque, target_phys_addr_t addr, { timerblock *tb = (timerblock *)opaque; int64_t val; - addr &= 0x1f; switch (addr) { case 0: /* Load */ return tb->load; @@ -126,7 +125,6 @@ static void timerblock_write(void *opaque, target_phys_addr_t addr, { timerblock *tb = (timerblock *)opaque; int64_t old; - addr &= 0x1f; switch (addr) { case 0: /* Load */ tb->load = value;