From patchwork Fri Mar 2 10:56:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7061 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 2F8CE23E4A for ; Fri, 2 Mar 2012 10:56:56 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id DF4AAA18452 for ; Fri, 2 Mar 2012 10:56:55 +0000 (UTC) Received: by iage36 with SMTP id e36so2860464iag.11 for ; Fri, 02 Mar 2012 02:56:55 -0800 (PST) Received: from mr.google.com ([10.50.187.168]) by 10.50.187.168 with SMTP id ft8mr1159462igc.55.1330685815407 (num_hops = 1); Fri, 02 Mar 2012 02:56:55 -0800 (PST) MIME-Version: 1.0 Received: by 10.50.187.168 with SMTP id ft8mr955710igc.55.1330685815345; Fri, 02 Mar 2012 02:56:55 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.53.18 with SMTP id k18csp6747ibg; Fri, 2 Mar 2012 02:56:54 -0800 (PST) Received: by 10.180.89.71 with SMTP id bm7mr3205986wib.20.1330685813809; Fri, 02 Mar 2012 02:56:53 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id g4si1227068wie.44.2012.03.02.02.56.52 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 02 Mar 2012 02:56:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1S3QAL-0001xc-Rs; Fri, 02 Mar 2012 10:56:49 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook Subject: [PATCH] target-arm: Clear IT bits when taking exceptions in v7M Date: Fri, 2 Mar 2012 10:56:49 +0000 Message-Id: <1330685809-7513-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 X-Gm-Message-State: ALoCoQkgSLKSmAEzzzSQPcH1uM6S+hAzzwMAEuYeOW8zlpUCV/dgD7tXRdDprCT8C6fYr4AFx5Ac When taking an exception for an M profile core, we must clear the IT bits. Since the IT bits are cached in env->condexec_bits we must clear them there: writing the bits in env->uncached_cpsr has no effect. (Reported as LP:944645.) Signed-off-by: Peter Maydell --- target-arm/helper.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 4929372..71fcc41 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -882,7 +882,8 @@ static void do_interrupt_v7m(CPUARMState *env) v7m_push(env, env->regs[1]); v7m_push(env, env->regs[0]); switch_v7m_sp(env, 0); - env->uncached_cpsr &= ~CPSR_IT; + /* Clear IT bits */ + env->condexec_bits = 0; env->regs[14] = lr; addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4); env->regs[15] = addr & 0xfffffffe;