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[81.2.115.146]) by mx.google.com with ESMTPS id n60si3607881weq.104.2012.02.24.03.38.23 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 24 Feb 2012 03:38:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1S0tTb-00077w-Sh; Fri, 24 Feb 2012 11:38:15 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Anthony Liguori , Paul Brook Subject: [PATCH] hw/arm11mpcore: Fix broken realview_mpcore/arm11mpcore_priv properties Date: Fri, 24 Feb 2012 11:38:15 +0000 Message-Id: <1330083495-27373-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 X-Gm-Message-State: ALoCoQmwOgQh5megF7gZNv0HYYnaUKH5i6LGK+TSFCsA8cIRT7IGp+7Ll3+61hYRd1LcxktZvKya Fix confusion in the Property arrays for the "arm11mpcore_priv" (per-CPU devices for the ARM11MPcore CPU) and "realview_mpcore" (realview-eb board specific device encapsulating CPU and some extra interrupt controllers) -- the num-irq property was defined on the wrong device and the mpcore_rirq_properties were defined as offsets in the wrong structure. The effect was that the realview-eb-mpcore machine would abort on startup trying to allocate an insane amount of memory. (This bug was introduced in the QOM conversion in commit 999e12bb.) Signed-off-by: Peter Maydell --- The trouble with doing all this as macro magic is that you end up repeating yourself and nothing errors out saying "you fool, when you typed the name of the object struct for the nth time you got it wrong"... hw/arm11mpcore.c | 20 ++++++++++---------- 1 files changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c index 102348b..c67b70f 100644 --- a/hw/arm11mpcore.c +++ b/hw/arm11mpcore.c @@ -202,16 +202,7 @@ static int realview_mpcore_init(SysBusDevice *dev) } static Property mpcore_rirq_properties[] = { - DEFINE_PROP_UINT32("num-cpu", mpcore_priv_state, num_cpu, 1), - /* The ARM11 MPCORE TRM says the on-chip controller may have - * anything from 0 to 224 external interrupt IRQ lines (with another - * 32 internal). We default to 32+32, which is the number provided by - * the ARM11 MPCore test chip in the Realview Versatile Express - * coretile. Other boards may differ and should set this property - * appropriately. Some Linux kernels may not boot if the hardware - * has more IRQ lines than the kernel expects. - */ - DEFINE_PROP_UINT32("num-irq", mpcore_priv_state, num_irq, 64), + DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), DEFINE_PROP_END_OF_LIST(), }; @@ -233,6 +224,15 @@ static TypeInfo mpcore_rirq_info = { static Property mpcore_priv_properties[] = { DEFINE_PROP_UINT32("num-cpu", mpcore_priv_state, num_cpu, 1), + /* The ARM11 MPCORE TRM says the on-chip controller may have + * anything from 0 to 224 external interrupt IRQ lines (with another + * 32 internal). We default to 32+32, which is the number provided by + * the ARM11 MPCore test chip in the Realview Versatile Express + * coretile. Other boards may differ and should set this property + * appropriately. Some Linux kernels may not boot if the hardware + * has more IRQ lines than the kernel expects. + */ + DEFINE_PROP_UINT32("num-irq", mpcore_priv_state, num_irq, 64), DEFINE_PROP_END_OF_LIST(), };