From patchwork Wed Feb 15 14:36:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 6792 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 6A7E223E01 for ; Wed, 15 Feb 2012 14:36:41 +0000 (UTC) Received: from mail-gx0-f180.google.com (mail-gx0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id 24E69A189DF for ; Wed, 15 Feb 2012 14:36:41 +0000 (UTC) Received: by ggnr1 with SMTP id r1so792537ggn.11 for ; Wed, 15 Feb 2012 06:36:40 -0800 (PST) MIME-Version: 1.0 Received: by 10.50.184.168 with SMTP id ev8mr41833660igc.29.1329316600511; Wed, 15 Feb 2012 06:36:40 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.66.135 with SMTP id n7cs12913ibi; Wed, 15 Feb 2012 06:36:39 -0800 (PST) Received: by 10.180.89.71 with SMTP id bm7mr8756979wib.20.1329316593894; Wed, 15 Feb 2012 06:36:33 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id u2si2632371weq.44.2012.02.15.06.36.33 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 15 Feb 2012 06:36:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1Rxfy8-0002pJ-La; Wed, 15 Feb 2012 14:36:28 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook , patches@linaro.org Subject: [PATCH v5 6/7] arm_boot: Pass base address of GIC CPU interface, not whole GIC Date: Wed, 15 Feb 2012 14:36:27 +0000 Message-Id: <1329316588-10830-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1329316588-10830-1-git-send-email-peter.maydell@linaro.org> References: <1329316588-10830-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlUSl4H3Fnm087IlxaB+28UlJ0fPWmzwOzpSJBwUnA86tXF+4nUx0taohY5nNzEs4wqOVPR The arm_boot secondary boot loader code needs the address of the GIC CPU interface. Obtaining this from the base address of the private peripheral region was possible for A9 and 11MPcore, but the A15 puts the GIC CPU interface in a different place. So make boards pass in the GIC CPU interface address directly. Signed-off-by: Peter Maydell --- hw/arm-misc.h | 2 +- hw/arm_boot.c | 8 ++++---- hw/realview.c | 12 +++++++----- hw/vexpress.c | 6 ++++-- 4 files changed, 16 insertions(+), 12 deletions(-) diff --git a/hw/arm-misc.h b/hw/arm-misc.h index 5e5204b..306013a 100644 --- a/hw/arm-misc.h +++ b/hw/arm-misc.h @@ -37,7 +37,7 @@ struct arm_boot_info { */ target_phys_addr_t smp_loader_start; target_phys_addr_t smp_bootreg_addr; - target_phys_addr_t smp_priv_base; + target_phys_addr_t gic_cpu_if_addr; int nb_cpus; int board_id; int (*atag_board)(const struct arm_boot_info *info, void *p); diff --git a/hw/arm_boot.c b/hw/arm_boot.c index 5f163fd..4637636 100644 --- a/hw/arm_boot.c +++ b/hw/arm_boot.c @@ -43,16 +43,16 @@ static uint32_t bootloader[] = { * location for the kernel secondary CPU entry point. */ static uint32_t smpboot[] = { - 0xe59f201c, /* ldr r2, privbase */ + 0xe59f201c, /* ldr r2, gic_cpu_if */ 0xe59f001c, /* ldr r0, startaddr */ 0xe3a01001, /* mov r1, #1 */ - 0xe5821100, /* str r1, [r2, #256] */ + 0xe5821000, /* str r1, [r2] */ 0xe320f003, /* wfi */ 0xe5901000, /* ldr r1, [r0] */ 0xe1110001, /* tst r1, r1 */ 0x0afffffb, /* beq */ 0xe12fff11, /* bx r1 */ - 0, /* privbase: Private memory region base address. */ + 0, /* gic_cpu_if: base address of GIC CPU interface */ 0 /* bootreg: Boot register address is held here */ }; @@ -61,7 +61,7 @@ static void default_write_secondary(CPUState *env, { int n; smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; - smpboot[ARRAY_SIZE(smpboot) - 2] = info->smp_priv_base; + smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; for (n = 0; n < ARRAY_SIZE(smpboot); n++) { smpboot[n] = tswap32(smpboot[n]); } diff --git a/hw/realview.c b/hw/realview.c index 8b0b03d..91c1b23 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -222,21 +222,23 @@ static void realview_init(ram_addr_t ram_size, sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000); if (is_mpcore) { + target_phys_addr_t periphbase; dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore"); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); qdev_init_nofail(dev); busdev = sysbus_from_qdev(dev); if (is_pb) { - realview_binfo.smp_priv_base = 0x1f000000; + periphbase = 0x1f000000; } else { - realview_binfo.smp_priv_base = 0x10100000; + periphbase = 0x10100000; } - sysbus_mmio_map(busdev, 0, realview_binfo.smp_priv_base); + sysbus_mmio_map(busdev, 0, periphbase); for (n = 0; n < smp_cpus; n++) { sysbus_connect_irq(busdev, n, cpu_irq[n]); } - sysbus_create_varargs("l2x0", realview_binfo.smp_priv_base + 0x2000, - NULL); + sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL); + /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ + realview_binfo.gic_cpu_if_addr = periphbase + 0x100; } else { uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; /* For now just create the nIRQ GIC, and ignore the others. */ diff --git a/hw/vexpress.c b/hw/vexpress.c index 43ad206..aae9d81 100644 --- a/hw/vexpress.c +++ b/hw/vexpress.c @@ -115,6 +115,7 @@ typedef void DBoardInitFn(const VEDBoardInfo *daughterboard, struct VEDBoardInfo { const target_phys_addr_t *motherboard_map; target_phys_addr_t loader_start; + const target_phys_addr_t gic_cpu_if_addr; DBoardInitFn *init; }; @@ -175,8 +176,7 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); qdev_init_nofail(dev); busdev = sysbus_from_qdev(dev); - vexpress_binfo.smp_priv_base = 0x1e000000; - sysbus_mmio_map(busdev, 0, vexpress_binfo.smp_priv_base); + sysbus_mmio_map(busdev, 0, 0x1e000000); for (n = 0; n < smp_cpus; n++) { sysbus_connect_irq(busdev, n, cpu_irq[n]); } @@ -214,6 +214,7 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, static const VEDBoardInfo a9_daughterboard = { .motherboard_map = motherboard_legacy_map, .loader_start = 0x60000000, + .gic_cpu_if_addr = 0x1e000100, .init = a9_daughterboard_init, }; @@ -316,6 +317,7 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard, vexpress_binfo.loader_start = daughterboard->loader_start; vexpress_binfo.smp_loader_start = map[VE_SRAM]; vexpress_binfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; + vexpress_binfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; arm_load_kernel(first_cpu, &vexpress_binfo); }