From patchwork Tue Jan 24 12:39:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 6373 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 960D523ECC for ; Tue, 24 Jan 2012 12:39:27 +0000 (UTC) Received: from mail-bk0-f52.google.com (mail-bk0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 84CC8A187AD for ; Tue, 24 Jan 2012 12:39:27 +0000 (UTC) Received: by mail-bk0-f52.google.com with SMTP id r19so3955104bka.11 for ; Tue, 24 Jan 2012 04:39:27 -0800 (PST) MIME-Version: 1.0 Received: by 10.204.200.197 with SMTP id ex5mr4740521bkb.128.1327408767317; Tue, 24 Jan 2012 04:39:27 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.204.130.220 with SMTP id u28cs99707bks; Tue, 24 Jan 2012 04:39:27 -0800 (PST) Received: by 10.236.146.4 with SMTP id q4mr17529495yhj.105.1327408765065; Tue, 24 Jan 2012 04:39:25 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id u30si16382920yhm.128.2012.01.24.04.39.23 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 24 Jan 2012 04:39:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1Rpfei-0000xf-TM; Tue, 24 Jan 2012 12:39:20 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [PATCH v2 3/9] hw/a15mpcore.c: Add Cortex-A15 private peripheral model Date: Tue, 24 Jan 2012 12:39:14 +0000 Message-Id: <1327408760-3666-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1327408760-3666-1-git-send-email-peter.maydell@linaro.org> References: <1327408760-3666-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQk/FFB982U/1znq18br+Sk2b+jxQTekzdXO5MtJJWM76Y4rUl5UIEb6q4vKAWXMLlLf5Z/k Add a model of the Cortex-A15 memory mapped private peripheral space. This is fairly simple because the only memory mapped bit of the A15 is the GIC. Note that we don't currently model a VGIC and therefore don't map the VGIC related bits of the GIC. Signed-off-by: Peter Maydell Reviewed-by: Andreas Färber --- Makefile.target | 2 +- hw/a15mpcore.c | 93 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+), 1 deletions(-) create mode 100644 hw/a15mpcore.c diff --git a/Makefile.target b/Makefile.target index 38b0c4d..dd0867f 100644 --- a/Makefile.target +++ b/Makefile.target @@ -336,7 +336,7 @@ obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o pl190.o obj-arm-y += versatile_pci.o obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o obj-arm-y += arm_l2x0.o -obj-arm-y += arm_mptimer.o +obj-arm-y += arm_mptimer.o a15mpcore.o obj-arm-y += armv7m.o armv7m_nvic.o stellaris.o pl022.o stellaris_enet.o obj-arm-y += highbank.o obj-arm-y += pl061.o diff --git a/hw/a15mpcore.c b/hw/a15mpcore.c new file mode 100644 index 0000000..fbbf2dc --- /dev/null +++ b/hw/a15mpcore.c @@ -0,0 +1,93 @@ +/* + * Cortex-A15MPCore internal peripheral emulation. + * + * Copyright (c) 2012 Linaro Limited. + * Written by Peter Maydell. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "sysbus.h" + +/* Configuration for arm_gic.c: + * max number of CPUs, how to ID current CPU + */ +#define NCPU 4 + +static inline int gic_get_current_cpu(void) +{ + return cpu_single_env->cpu_index; +} + +#include "arm_gic.c" + +/* A15MP private memory region. */ + +typedef struct A15MPPrivState { + gic_state gic; + uint32_t num_cpu; + uint32_t num_irq; + MemoryRegion container; +} A15MPPrivState; + +static int a15mp_priv_init(SysBusDevice *dev) +{ + A15MPPrivState *s = FROM_SYSBUSGIC(A15MPPrivState, dev); + + if (s->num_cpu > NCPU) { + hw_error("a15mp_priv_init: num-cpu may not be more than %d\n", NCPU); + } + + gic_init(&s->gic, s->num_cpu, s->num_irq); + + /* Memory map (addresses are offsets from PERIPHBASE): + * 0x0000-0x0fff -- reserved + * 0x1000-0x1fff -- GIC Distributor + * 0x2000-0x2fff -- GIC CPU interface + * 0x4000-0x4fff -- GIC virtual interface control (not modelled) + * 0x5000-0x5fff -- GIC virtual interface control (not modelled) + * 0x6000-0x7fff -- GIC virtual CPU interface (not modelled) + */ + memory_region_init(&s->container, "a15mp-priv-container", 0x8000); + memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem); + memory_region_add_subregion(&s->container, 0x2000, &s->gic.cpuiomem[0]); + + sysbus_init_mmio(dev, &s->container); + return 0; +} + +static SysBusDeviceInfo a15mp_priv_info = { + .init = a15mp_priv_init, + .qdev.name = "a15mpcore_priv", + .qdev.size = sizeof(A15MPPrivState), + /* We currently have no savable state outside the common GIC state */ + .qdev.props = (Property[]) { + DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), + /* The Cortex-A15MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 64+32, which + * is the number provided by the Cortex-A15MP test chip in the + * Versatile Express A15 development board. + * Other boards may differ and should set this property appropriately. + */ + DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 96), + DEFINE_PROP_END_OF_LIST(), + } +}; + +static void a15mp_register_devices(void) +{ + sysbus_register_withprop(&a15mp_priv_info); +} + +device_init(a15mp_register_devices)