From patchwork Fri Jan 13 20:52:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 6215 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 419CD23E01 for ; Fri, 13 Jan 2012 20:56:34 +0000 (UTC) Received: from mail-bk0-f52.google.com (mail-bk0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 31FA2A18309 for ; Fri, 13 Jan 2012 20:56:34 +0000 (UTC) Received: by mail-bk0-f52.google.com with SMTP id zu5so3285488bkb.11 for ; Fri, 13 Jan 2012 12:56:34 -0800 (PST) Received: by 10.204.38.80 with SMTP id a16mr1059593bke.99.1326488193946; Fri, 13 Jan 2012 12:56:33 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.82.144 with SMTP id ac16cs39016bkc; Fri, 13 Jan 2012 12:56:33 -0800 (PST) Received: by 10.180.75.7 with SMTP id y7mr4870082wiv.2.1326488192403; Fri, 13 Jan 2012 12:56:32 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id u30si5816590weq.38.2012.01.13.12.56.32 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 13 Jan 2012 12:56:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1Rlo7F-0003FT-9K; Fri, 13 Jan 2012 20:52:49 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, android-virt@lists.cs.columbia.edu Subject: [PATCH 01/12] vexpress, realview: Add (dummy) L2 cache controller Date: Fri, 13 Jan 2012 20:52:38 +0000 Message-Id: <1326487969-12462-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1326487969-12462-1-git-send-email-peter.maydell@linaro.org> References: <1326487969-12462-1-git-send-email-peter.maydell@linaro.org> Instantiate the L2 cache controller on the ARM devboards which have one, since we have a dummy model of it now. Note that the only non-MP board with an L2x0 is the PB1176, which we don't model. Signed-off-by: Peter Maydell --- hw/realview.c | 2 ++ hw/vexpress.c | 1 + 2 files changed, 3 insertions(+), 0 deletions(-) diff --git a/hw/realview.c b/hw/realview.c index d4191e9..e52babc 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -225,6 +225,8 @@ static void realview_init(ram_addr_t ram_size, for (n = 0; n < smp_cpus; n++) { sysbus_connect_irq(busdev, n, cpu_irq[n]); } + sysbus_create_varargs("l2x0", realview_binfo.smp_priv_base + 0x2000, + NULL); } else { uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; /* For now just create the nIRQ GIC, and ignore the others. */ diff --git a/hw/vexpress.c b/hw/vexpress.c index 0f39d8d..613be65 100644 --- a/hw/vexpress.c +++ b/hw/vexpress.c @@ -180,6 +180,7 @@ static void vexpress_a9_init(ram_addr_t ram_size, /* 0x100ec000 TrustZone Address Space Controller */ /* 0x10200000 CoreSight debug APB */ /* 0x1e00a000 PL310 L2 Cache Controller */ + sysbus_create_varargs("l2x0", 0x1e00a000, NULL); /* CS0: NOR0 flash : 0x40000000 .. 0x44000000 */ /* CS4: NOR1 flash : 0x44000000 .. 0x48000000 */