From patchwork Wed Jan 4 17:01:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 6050 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 2659823F7F for ; Wed, 4 Jan 2012 17:01:46 +0000 (UTC) Received: from mail-bk0-f52.google.com (mail-bk0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 09D43A181D3 for ; Wed, 4 Jan 2012 17:01:46 +0000 (UTC) Received: by bke17 with SMTP id 17so63993bke.11 for ; Wed, 04 Jan 2012 09:01:45 -0800 (PST) Received: by 10.204.133.207 with SMTP id g15mr13158840bkt.17.1325696505682; Wed, 04 Jan 2012 09:01:45 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.82.144 with SMTP id ac16cs375618bkc; Wed, 4 Jan 2012 09:01:45 -0800 (PST) Received: by 10.227.204.208 with SMTP id fn16mr56800588wbb.6.1325696504677; Wed, 04 Jan 2012 09:01:44 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id eo7si17636640wbb.61.2012.01.04.09.01.44 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 04 Jan 2012 09:01:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1RiUDe-000692-D8; Wed, 04 Jan 2012 17:01:42 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Mark Langsdorf Subject: [PATCH] vexpress, realview: Add (dummy) L2 cache controller Date: Wed, 4 Jan 2012 17:01:42 +0000 Message-Id: <1325696502-23597-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 Instantiate the L2 cache controller on the ARM devboards which have one, since we have a dummy model of it now. Note that the only non-MP board with an L2x0 is the PB1176, which we don't model. Signed-off-by: Peter Maydell --- This is intended to be applied after the l2x0 implementation patch, obviously. hw/realview.c | 2 ++ hw/vexpress.c | 1 + 2 files changed, 3 insertions(+), 0 deletions(-) diff --git a/hw/realview.c b/hw/realview.c index 750a279..fe75b03 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -223,6 +223,8 @@ static void realview_init(ram_addr_t ram_size, for (n = 0; n < smp_cpus; n++) { sysbus_connect_irq(busdev, n, cpu_irq[n]); } + sysbus_create_varargs("l2x0", realview_binfo.smp_priv_base + 0x2000, + NULL); } else { uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; /* For now just create the nIRQ GIC, and ignore the others. */ diff --git a/hw/vexpress.c b/hw/vexpress.c index 08c93d5..b8d69bb 100644 --- a/hw/vexpress.c +++ b/hw/vexpress.c @@ -176,6 +176,7 @@ static void vexpress_a9_init(ram_addr_t ram_size, /* 0x100ec000 TrustZone Address Space Controller */ /* 0x10200000 CoreSight debug APB */ /* 0x1e00a000 PL310 L2 Cache Controller */ + sysbus_create_varargs("l2x0", 0x1e00a000, NULL); /* CS0: NOR0 flash : 0x40000000 .. 0x44000000 */ /* CS4: NOR1 flash : 0x44000000 .. 0x48000000 */