From patchwork Tue Dec 20 18:11:35 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 5901 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 26EA223E03 for ; Tue, 20 Dec 2011 18:11:45 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id 120CCA1821A for ; Tue, 20 Dec 2011 18:11:45 +0000 (UTC) Received: by mail-ey0-f180.google.com with SMTP id c11so3641659eaa.11 for ; Tue, 20 Dec 2011 10:11:45 -0800 (PST) Received: by 10.204.136.194 with SMTP id s2mr1249947bkt.96.1324404704864; Tue, 20 Dec 2011 10:11:44 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.82.144 with SMTP id ac16cs18992bkc; Tue, 20 Dec 2011 10:11:44 -0800 (PST) Received: by 10.68.75.130 with SMTP id c2mr4727980pbw.93.1324404702306; Tue, 20 Dec 2011 10:11:42 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id mj2si2811749pbc.165.2011.12.20.10.11.40 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 20 Dec 2011 10:11:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1Rd4A4-0008AX-Fy; Tue, 20 Dec 2011 18:11:36 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Andrzej Zaborowski , =?UTF-8?q?Juha=20Riihim=C3=A4ki?= , Riku Voipio Subject: [PATCH 5/6] hw/omap1.c: Separate clkm from omap_mpu_state Date: Tue, 20 Dec 2011 18:11:35 +0000 Message-Id: <1324404696-31368-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1324404696-31368-1-git-send-email-peter.maydell@linaro.org> References: <1324404696-31368-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 From: Juha Riihimäki Signed-off-by: Juha Riihimäki [Riku Voipio: Fixes and restructuring patchset] Signed-off-by: Riku Voipio [Peter Maydell: More fixes and cleanups for upstream submission] Signed-off-by: Peter Maydell --- hw/omap.h | 16 +------- hw/omap1.c | 127 ++++++++++++++++++++++++++++++++++-------------------------- 2 files changed, 73 insertions(+), 70 deletions(-) diff --git a/hw/omap.h b/hw/omap.h index 60fa34c..17b4312 100644 --- a/hw/omap.h +++ b/hw/omap.h @@ -907,21 +907,7 @@ struct omap_mpu_state_s { struct dpll_ctl_s *dpll[3]; omap_clk clks; - struct { - int cold_start; - int clocking_scheme; - uint16_t arm_ckctl; - uint16_t arm_idlect1; - uint16_t arm_idlect2; - uint16_t arm_ewupct; - uint16_t arm_rstct1; - uint16_t arm_rstct2; - uint16_t arm_ckout1; - int dpll1_mode; - uint16_t dsp_idlect1; - uint16_t dsp_idlect2; - uint16_t dsp_rstct2; - } clkm; + struct omap_clkm_s *clkm; /* OMAP2-only peripherals */ struct omap_l4_s *l4; diff --git a/hw/omap1.c b/hw/omap1.c index 6ab9192..5fc67e9 100644 --- a/hw/omap1.c +++ b/hw/omap1.c @@ -1429,6 +1429,22 @@ static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory, } /* MPU Clock/Reset/Power Mode Control */ +struct omap_clkm_s { + int cold_start; + int clocking_scheme; + uint16_t arm_ckctl; + uint16_t arm_idlect1; + uint16_t arm_idlect2; + uint16_t arm_ewupct; + uint16_t arm_rstct1; + uint16_t arm_rstct2; + uint16_t arm_ckout1; + int dpll1_mode; + uint16_t dsp_idlect1; + uint16_t dsp_idlect2; + uint16_t dsp_rstct2; +}; + static uint64_t omap_clkm_read(void *opaque, target_phys_addr_t addr, unsigned size) { @@ -1440,28 +1456,28 @@ static uint64_t omap_clkm_read(void *opaque, target_phys_addr_t addr, switch (addr) { case 0x00: /* ARM_CKCTL */ - return s->clkm.arm_ckctl; + return s->clkm->arm_ckctl; case 0x04: /* ARM_IDLECT1 */ - return s->clkm.arm_idlect1; + return s->clkm->arm_idlect1; case 0x08: /* ARM_IDLECT2 */ - return s->clkm.arm_idlect2; + return s->clkm->arm_idlect2; case 0x0c: /* ARM_EWUPCT */ - return s->clkm.arm_ewupct; + return s->clkm->arm_ewupct; case 0x10: /* ARM_RSTCT1 */ - return s->clkm.arm_rstct1; + return s->clkm->arm_rstct1; case 0x14: /* ARM_RSTCT2 */ - return s->clkm.arm_rstct2; + return s->clkm->arm_rstct2; case 0x18: /* ARM_SYSST */ - return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; + return (s->clkm->clocking_scheme << 11) | s->clkm->cold_start; case 0x1c: /* ARM_CKOUT1 */ - return s->clkm.arm_ckout1; + return s->clkm->arm_ckout1; case 0x20: /* ARM_CKOUT2 */ break; @@ -1647,33 +1663,33 @@ static void omap_clkm_write(void *opaque, target_phys_addr_t addr, switch (addr) { case 0x00: /* ARM_CKCTL */ - diff = s->clkm.arm_ckctl ^ value; - s->clkm.arm_ckctl = value & 0x7fff; + diff = s->clkm->arm_ckctl ^ value; + s->clkm->arm_ckctl = value & 0x7fff; omap_clkm_ckctl_update(s, diff, value); return; case 0x04: /* ARM_IDLECT1 */ - diff = s->clkm.arm_idlect1 ^ value; - s->clkm.arm_idlect1 = value & 0x0fff; + diff = s->clkm->arm_idlect1 ^ value; + s->clkm->arm_idlect1 = value & 0x0fff; omap_clkm_idlect1_update(s, diff, value); return; case 0x08: /* ARM_IDLECT2 */ - diff = s->clkm.arm_idlect2 ^ value; - s->clkm.arm_idlect2 = value & 0x07ff; + diff = s->clkm->arm_idlect2 ^ value; + s->clkm->arm_idlect2 = value & 0x07ff; omap_clkm_idlect2_update(s, diff, value); return; case 0x0c: /* ARM_EWUPCT */ - s->clkm.arm_ewupct = value & 0x003f; + s->clkm->arm_ewupct = value & 0x003f; return; case 0x10: /* ARM_RSTCT1 */ - diff = s->clkm.arm_rstct1 ^ value; - s->clkm.arm_rstct1 = value & 0x0007; + diff = s->clkm->arm_rstct1 ^ value; + s->clkm->arm_rstct1 = value & 0x0007; if (value & 9) { qemu_system_reset_request(); - s->clkm.cold_start = 0xa; + s->clkm->cold_start = 0xa; } if (diff & ~value & 4) { /* DSP_RST */ omap_mpui_reset(s); @@ -1687,21 +1703,21 @@ static void omap_clkm_write(void *opaque, target_phys_addr_t addr, return; case 0x14: /* ARM_RSTCT2 */ - s->clkm.arm_rstct2 = value & 0x0001; + s->clkm->arm_rstct2 = value & 0x0001; return; case 0x18: /* ARM_SYSST */ - if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { - s->clkm.clocking_scheme = (value >> 11) & 7; + if ((s->clkm->clocking_scheme ^ (value >> 11)) & 7) { + s->clkm->clocking_scheme = (value >> 11) & 7; printf("%s: clocking scheme set to %s\n", __FUNCTION__, - clkschemename[s->clkm.clocking_scheme]); + clkschemename[s->clkm->clocking_scheme]); } - s->clkm.cold_start &= value & 0x3f; + s->clkm->cold_start &= value & 0x3f; return; case 0x1c: /* ARM_CKOUT1 */ - diff = s->clkm.arm_ckout1 ^ value; - s->clkm.arm_ckout1 = value & 0x003f; + diff = s->clkm->arm_ckout1 ^ value; + s->clkm->arm_ckout1 = value & 0x003f; omap_clkm_ckout1_update(s, diff, value); return; @@ -1728,16 +1744,16 @@ static uint64_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr, switch (addr) { case 0x04: /* DSP_IDLECT1 */ - return s->clkm.dsp_idlect1; + return s->clkm->dsp_idlect1; case 0x08: /* DSP_IDLECT2 */ - return s->clkm.dsp_idlect2; + return s->clkm->dsp_idlect2; case 0x14: /* DSP_RSTCT2 */ - return s->clkm.dsp_rstct2; + return s->clkm->dsp_rstct2; case 0x18: /* DSP_SYSST */ - return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | + return (s->clkm->clocking_scheme << 11) | s->clkm->cold_start | (s->env->halted << 6); /* Quite useless... */ } @@ -1773,23 +1789,23 @@ static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr, switch (addr) { case 0x04: /* DSP_IDLECT1 */ - diff = s->clkm.dsp_idlect1 ^ value; - s->clkm.dsp_idlect1 = value & 0x01f7; + diff = s->clkm->dsp_idlect1 ^ value; + s->clkm->dsp_idlect1 = value & 0x01f7; omap_clkdsp_idlect1_update(s, diff, value); break; case 0x08: /* DSP_IDLECT2 */ - s->clkm.dsp_idlect2 = value & 0x0037; - diff = s->clkm.dsp_idlect1 ^ value; + s->clkm->dsp_idlect2 = value & 0x0037; + diff = s->clkm->dsp_idlect1 ^ value; omap_clkdsp_idlect2_update(s, diff, value); break; case 0x14: /* DSP_RSTCT2 */ - s->clkm.dsp_rstct2 = value & 0x0001; + s->clkm->dsp_rstct2 = value & 0x0001; break; case 0x18: /* DSP_SYSST */ - s->clkm.cold_start &= value & 0x3f; + s->clkm->cold_start &= value & 0x3f; break; default: @@ -1806,24 +1822,24 @@ static const MemoryRegionOps omap_clkdsp_ops = { static void omap_clkm_reset(struct omap_mpu_state_s *s) { if (s->wdt && s->wdt->reset) - s->clkm.cold_start = 0x6; - s->clkm.clocking_scheme = 0; + s->clkm->cold_start = 0x6; + s->clkm->clocking_scheme = 0; omap_clkm_ckctl_update(s, ~0, 0x3000); - s->clkm.arm_ckctl = 0x3000; - omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); - s->clkm.arm_idlect1 = 0x0400; - omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); - s->clkm.arm_idlect2 = 0x0100; - s->clkm.arm_ewupct = 0x003f; - s->clkm.arm_rstct1 = 0x0000; - s->clkm.arm_rstct2 = 0x0000; - s->clkm.arm_ckout1 = 0x0015; - s->clkm.dpll1_mode = 0x2002; - omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); - s->clkm.dsp_idlect1 = 0x0040; + s->clkm->arm_ckctl = 0x3000; + omap_clkm_idlect1_update(s, s->clkm->arm_idlect1 ^ 0x0400, 0x0400); + s->clkm->arm_idlect1 = 0x0400; + omap_clkm_idlect2_update(s, s->clkm->arm_idlect2 ^ 0x0100, 0x0100); + s->clkm->arm_idlect2 = 0x0100; + s->clkm->arm_ewupct = 0x003f; + s->clkm->arm_rstct1 = 0x0000; + s->clkm->arm_rstct2 = 0x0000; + s->clkm->arm_ckout1 = 0x0015; + s->clkm->dpll1_mode = 0x2002; + omap_clkdsp_idlect1_update(s, s->clkm->dsp_idlect1 ^ 0x0040, 0x0040); + s->clkm->dsp_idlect1 = 0x0040; omap_clkdsp_idlect2_update(s, ~0, 0x0000); - s->clkm.dsp_idlect2 = 0x0000; - s->clkm.dsp_rstct2 = 0x0000; + s->clkm->dsp_idlect2 = 0x0000; + s->clkm->dsp_rstct2 = 0x0000; } static void omap_clkm_init(MemoryRegion *memory, target_phys_addr_t mpu_base, @@ -1834,11 +1850,12 @@ static void omap_clkm_init(MemoryRegion *memory, target_phys_addr_t mpu_base, memory_region_init_io(&s->clkdsp_iomem, &omap_clkdsp_ops, s, "omap-clkdsp", 0x1000); - s->clkm.arm_idlect1 = 0x03ff; - s->clkm.arm_idlect2 = 0x0100; - s->clkm.dsp_idlect1 = 0x0002; + s->clkm = g_malloc0(sizeof(*(s->clkm))); + s->clkm->arm_idlect1 = 0x03ff; + s->clkm->arm_idlect2 = 0x0100; + s->clkm->dsp_idlect1 = 0x0002; omap_clkm_reset(s); - s->clkm.cold_start = 0x3a; + s->clkm->cold_start = 0x3a; memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem); memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem);