From patchwork Tue Dec 20 18:11:32 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 5900 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 0F5F923E03 for ; Tue, 20 Dec 2011 18:11:44 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id 0044CA1821A for ; Tue, 20 Dec 2011 18:11:43 +0000 (UTC) Received: by mail-ey0-f180.google.com with SMTP id c11so3641659eaa.11 for ; Tue, 20 Dec 2011 10:11:43 -0800 (PST) Received: by 10.205.138.136 with SMTP id is8mr1260709bkc.35.1324404703786; Tue, 20 Dec 2011 10:11:43 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.82.144 with SMTP id ac16cs18991bkc; Tue, 20 Dec 2011 10:11:43 -0800 (PST) Received: by 10.101.129.24 with SMTP id g24mr1692126ann.31.1324404701637; Tue, 20 Dec 2011 10:11:41 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id b3si1420804ank.39.2011.12.20.10.11.40 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 20 Dec 2011 10:11:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1Rd4A4-0008AR-Dx; Tue, 20 Dec 2011 18:11:36 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Andrzej Zaborowski , =?UTF-8?q?Juha=20Riihim=C3=A4ki?= , Riku Voipio Subject: [PATCH 2/6] hw/omap1.c: Separate PWL from omap_mpu_state Date: Tue, 20 Dec 2011 18:11:32 +0000 Message-Id: <1324404696-31368-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1324404696-31368-1-git-send-email-peter.maydell@linaro.org> References: <1324404696-31368-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 From: Juha Riihimäki Signed-off-by: Juha Riihimäki [Riku Voipio: Fixes and restructuring patchset] Signed-off-by: Riku Voipio [Peter Maydell: More fixes and cleanups for upstream submission] Signed-off-by: Peter Maydell --- hw/omap.h | 8 +------- hw/omap1.c | 60 ++++++++++++++++++++++++++++++++++++------------------------ 2 files changed, 37 insertions(+), 31 deletions(-) diff --git a/hw/omap.h b/hw/omap.h index 5fe33db..851ad46 100644 --- a/hw/omap.h +++ b/hw/omap.h @@ -829,7 +829,6 @@ struct omap_mpu_state_s { MemoryRegion tcmi_iomem; MemoryRegion clkm_iomem; MemoryRegion clkdsp_iomem; - MemoryRegion pwl_iomem; MemoryRegion pwt_iomem; MemoryRegion mpui_io_iomem; MemoryRegion tap_iomem; @@ -867,12 +866,7 @@ struct omap_mpu_state_s { struct omap_uwire_s *microwire; - struct { - uint8_t output; - uint8_t level; - uint8_t enable; - int clk; - } pwl; + struct omap_pwl_s *pwl; struct { uint8_t frc; diff --git a/hw/omap1.c b/hw/omap1.c index dddac92..ccc6ecf 100644 --- a/hw/omap1.c +++ b/hw/omap1.c @@ -2289,12 +2289,20 @@ void omap_uwire_attach(struct omap_uwire_s *s, } /* Pseudonoise Pulse-Width Light Modulator */ -static void omap_pwl_update(struct omap_mpu_state_s *s) +struct omap_pwl_s { + MemoryRegion iomem; + uint8_t output; + uint8_t level; + uint8_t enable; + int clk; +}; + +static void omap_pwl_update(struct omap_pwl_s *s) { - int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0; + int output = (s->clk && s->enable) ? s->level : 0; - if (output != s->pwl.output) { - s->pwl.output = output; + if (output != s->output) { + s->output = output; printf("%s: Backlight now at %i/256\n", __FUNCTION__, output); } } @@ -2302,7 +2310,7 @@ static void omap_pwl_update(struct omap_mpu_state_s *s) static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr, unsigned size) { - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; + struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; int offset = addr & OMAP_MPUI_REG_MASK; if (size != 1) { @@ -2311,9 +2319,9 @@ static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr, switch (offset) { case 0x00: /* PWL_LEVEL */ - return s->pwl.level; + return s->level; case 0x04: /* PWL_CTRL */ - return s->pwl.enable; + return s->enable; } OMAP_BAD_REG(addr); return 0; @@ -2322,7 +2330,7 @@ static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr, static void omap_pwl_write(void *opaque, target_phys_addr_t addr, uint64_t value, unsigned size) { - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; + struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; int offset = addr & OMAP_MPUI_REG_MASK; if (size != 1) { @@ -2331,11 +2339,11 @@ static void omap_pwl_write(void *opaque, target_phys_addr_t addr, switch (offset) { case 0x00: /* PWL_LEVEL */ - s->pwl.level = value; + s->level = value; omap_pwl_update(s); break; case 0x04: /* PWL_CTRL */ - s->pwl.enable = value & 1; + s->enable = value & 1; omap_pwl_update(s); break; default: @@ -2350,34 +2358,37 @@ static const MemoryRegionOps omap_pwl_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static void omap_pwl_reset(struct omap_mpu_state_s *s) +static void omap_pwl_reset(struct omap_pwl_s *s) { - s->pwl.output = 0; - s->pwl.level = 0; - s->pwl.enable = 0; - s->pwl.clk = 1; + s->output = 0; + s->level = 0; + s->enable = 0; + s->clk = 1; omap_pwl_update(s); } static void omap_pwl_clk_update(void *opaque, int line, int on) { - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; + struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; - s->pwl.clk = on; + s->clk = on; omap_pwl_update(s); } -static void omap_pwl_init(MemoryRegion *system_memory, - target_phys_addr_t base, struct omap_mpu_state_s *s, - omap_clk clk) +static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory, + target_phys_addr_t base, + omap_clk clk) { + struct omap_pwl_s *s = g_malloc0(sizeof(*s)); + omap_pwl_reset(s); - memory_region_init_io(&s->pwl_iomem, &omap_pwl_ops, s, + memory_region_init_io(&s->iomem, &omap_pwl_ops, s, "omap-pwl", 0x800); - memory_region_add_subregion(system_memory, base, &s->pwl_iomem); + memory_region_add_subregion(system_memory, base, &s->iomem); omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]); + return s; } /* Pulse-Width Tone module */ @@ -3667,7 +3678,7 @@ static void omap1_mpu_reset(void *opaque) omap_mmc_reset(mpu->mmc); omap_mpuio_reset(mpu->mpuio); omap_uwire_reset(mpu->microwire); - omap_pwl_reset(mpu); + omap_pwl_reset(mpu->pwl); omap_pwt_reset(mpu); omap_i2c_reset(mpu->i2c[0]); omap_rtc_reset(mpu->rtc); @@ -3961,7 +3972,8 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX), s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck")); - omap_pwl_init(system_memory, 0xfffb5800, s, omap_findclk(s, "armxor_ck")); + s->pwl = omap_pwl_init(system_memory, 0xfffb5800, + omap_findclk(s, "armxor_ck")); omap_pwt_init(system_memory, 0xfffb6000, s, omap_findclk(s, "armxor_ck")); s->i2c[0] = omap_i2c_init(system_memory, 0xfffb3800,