From patchwork Mon Dec 5 16:40:18 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 5461 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id E754823E2C for ; Mon, 5 Dec 2011 16:40:27 +0000 (UTC) Received: from mail-lpp01m010-f52.google.com (mail-lpp01m010-f52.google.com [209.85.215.52]) by fiordland.canonical.com (Postfix) with ESMTP id CC2E2A18251 for ; Mon, 5 Dec 2011 16:40:27 +0000 (UTC) Received: by mail-lpp01m010-f52.google.com with SMTP id m6so354071lag.11 for ; Mon, 05 Dec 2011 08:40:27 -0800 (PST) Received: by 10.152.106.115 with SMTP id gt19mr6568124lab.27.1323103227711; Mon, 05 Dec 2011 08:40:27 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.41.198 with SMTP id h6cs266701lal; Mon, 5 Dec 2011 08:40:27 -0800 (PST) Received: by 10.180.72.146 with SMTP id d18mr13906428wiv.12.1323103224667; Mon, 05 Dec 2011 08:40:24 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id dt17si14235241bkb.18.2011.12.05.08.40.23 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 05 Dec 2011 08:40:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1RXbaW-0000Qz-RU; Mon, 05 Dec 2011 16:40:20 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Bill Carson Subject: [PATCH 5/7] hw/mpcore: Clean up mpcore_priv_read/write as they are now SCU only Date: Mon, 5 Dec 2011 16:40:18 +0000 Message-Id: <1323103220-1636-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1323103220-1636-1-git-send-email-peter.maydell@linaro.org> References: <1323103220-1636-1-git-send-email-peter.maydell@linaro.org> The only code left in mpcore_priv_read and mpcore_priv_write is now the implementation of the SCU registers. Clean up by renaming functions and removing some unnecessary conditionals to make this clearer. Signed-off-by: Peter Maydell --- hw/mpcore.c | 73 +++++++++++++++++++++++++---------------------------------- 1 files changed, 31 insertions(+), 42 deletions(-) diff --git a/hw/mpcore.c b/hw/mpcore.c index a0af1ad..670d7e5 100644 --- a/hw/mpcore.c +++ b/hw/mpcore.c @@ -36,59 +36,49 @@ typedef struct mpcore_priv_state { /* Per-CPU private memory mapped IO. */ -static uint64_t mpcore_priv_read(void *opaque, target_phys_addr_t offset, - unsigned size) +static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset, + unsigned size) { mpcore_priv_state *s = (mpcore_priv_state *)opaque; int id; offset &= 0xff; - if (offset < 0x100) { - /* SCU */ - switch (offset) { - case 0x00: /* Control. */ - return s->scu_control; - case 0x04: /* Configuration. */ - id = ((1 << s->num_cpu) - 1) << 4; - return id | (s->num_cpu - 1); - case 0x08: /* CPU status. */ - return 0; - case 0x0c: /* Invalidate all. */ - return 0; - default: - goto bad_reg; - } + /* SCU */ + switch (offset) { + case 0x00: /* Control. */ + return s->scu_control; + case 0x04: /* Configuration. */ + id = ((1 << s->num_cpu) - 1) << 4; + return id | (s->num_cpu - 1); + case 0x08: /* CPU status. */ + return 0; + case 0x0c: /* Invalidate all. */ + return 0; + default: + hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); } -bad_reg: - hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); - return 0; } -static void mpcore_priv_write(void *opaque, target_phys_addr_t offset, - uint64_t value, unsigned size) +static void mpcore_scu_write(void *opaque, target_phys_addr_t offset, + uint64_t value, unsigned size) { mpcore_priv_state *s = (mpcore_priv_state *)opaque; offset &= 0xff; - if (offset < 0x100) { - /* SCU */ - switch (offset) { - case 0: /* Control register. */ - s->scu_control = value & 1; - break; - case 0x0c: /* Invalidate all. */ - /* This is a no-op as cache is not emulated. */ - break; - default: - goto bad_reg; - } + /* SCU */ + switch (offset) { + case 0: /* Control register. */ + s->scu_control = value & 1; + break; + case 0x0c: /* Invalidate all. */ + /* This is a no-op as cache is not emulated. */ + break; + default: + hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); } - return; -bad_reg: - hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); } -static const MemoryRegionOps mpcore_priv_ops = { - .read = mpcore_priv_read, - .write = mpcore_priv_write, +static const MemoryRegionOps mpcore_scu_ops = { + .read = mpcore_scu_read, + .write = mpcore_scu_write, .endianness = DEVICE_NATIVE_ENDIAN, }; @@ -106,8 +96,7 @@ static void mpcore_priv_map_setup(mpcore_priv_state *s) int i; SysBusDevice *busdev = sysbus_from_qdev(s->mptimer); memory_region_init(&s->container, "mpcode-priv-container", 0x2000); - memory_region_init_io(&s->iomem, &mpcore_priv_ops, s, "mpcode-priv", - 0x100); + memory_region_init_io(&s->iomem, &mpcore_scu_ops, s, "mpcore-scu", 0x100); memory_region_add_subregion(&s->container, 0, &s->iomem); /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs * at 0x200, 0x300...