From patchwork Mon Dec 5 16:40:15 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 5464 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 360D223E0C for ; Mon, 5 Dec 2011 16:40:30 +0000 (UTC) Received: from mail-lpp01m010-f52.google.com (mail-lpp01m010-f52.google.com [209.85.215.52]) by fiordland.canonical.com (Postfix) with ESMTP id 1B41BA18315 for ; Mon, 5 Dec 2011 16:40:30 +0000 (UTC) Received: by mail-lpp01m010-f52.google.com with SMTP id m6so354087lag.11 for ; Mon, 05 Dec 2011 08:40:30 -0800 (PST) Received: by 10.152.105.67 with SMTP id gk3mr6539956lab.48.1323103229986; Mon, 05 Dec 2011 08:40:29 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.41.198 with SMTP id h6cs266708lal; Mon, 5 Dec 2011 08:40:29 -0800 (PST) Received: by 10.68.26.4 with SMTP id h4mr24398122pbg.96.1323103227508; Mon, 05 Dec 2011 08:40:27 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTP id mj2si24029230pbc.165.2011.12.05.08.40.25; Mon, 05 Dec 2011 08:40:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1RXbaW-0000Qt-Pf; Mon, 05 Dec 2011 16:40:20 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Bill Carson Subject: [PATCH 2/7] hw/arm_gic: Expose GIC CPU interfaces as sysbus memory regions Date: Mon, 5 Dec 2011 16:40:15 +0000 Message-Id: <1323103220-1636-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1323103220-1636-1-git-send-email-peter.maydell@linaro.org> References: <1323103220-1636-1-git-send-email-peter.maydell@linaro.org> Expose the ARM GIC CPU interfaces as memory regions, rather than just providing read and write functions for them. Signed-off-by: Peter Maydell --- hw/arm_gic.c | 75 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 74 insertions(+), 1 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index f3f3516..10d4028 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -103,7 +103,14 @@ typedef struct gic_state int num_cpu; #endif - MemoryRegion iomem; + MemoryRegion iomem; /* Distributor */ +#ifndef NVIC + /* This is just so we can have an opaque pointer which identifies + * both this GIC and which CPU interface we should be accessing. + */ + struct gic_state *backref[NCPU]; + MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */ +#endif } gic_state; /* TODO: Many places that call this routine could be optimized. */ @@ -624,6 +631,54 @@ static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value) } gic_update(s); } + +/* Wrappers to read/write the GIC CPU interface for the current CPU */ +static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr, + unsigned size) +{ + gic_state *s = (gic_state *)opaque; + return gic_cpu_read(s, gic_get_current_cpu(), addr & 0xff); +} + +static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr, + uint64_t value, unsigned size) +{ + gic_state *s = (gic_state *)opaque; + gic_cpu_write(s, gic_get_current_cpu(), addr & 0xff, value); +} + +/* Wrappers to read/write the GIC CPU interface for a specific CPU. + * These just decode the opaque pointer into gic_state* + cpu id. + */ +static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr, + unsigned size) +{ + gic_state **backref = (gic_state **)opaque; + gic_state *s = *backref; + int id = (backref - s->backref); + return gic_cpu_read(s, id, addr & 0xff); +} + +static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr, + uint64_t value, unsigned size) +{ + gic_state **backref = (gic_state **)opaque; + gic_state *s = *backref; + int id = (backref - s->backref); + gic_cpu_write(s, id, addr & 0xff, value); +} + +static const MemoryRegionOps gic_thiscpu_ops = { + .read = gic_thiscpu_read, + .write = gic_thiscpu_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static const MemoryRegionOps gic_cpu_ops = { + .read = gic_do_cpu_read, + .write = gic_do_cpu_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; #endif static void gic_reset(gic_state *s) @@ -743,6 +798,24 @@ static void gic_init(gic_state *s) sysbus_init_irq(&s->busdev, &s->parent_irq[i]); } memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000); +#ifndef NVIC + /* Memory regions for the CPU interfaces (NVIC doesn't have these): + * a region for "CPU interface for this core", then a region for + * "CPU interface for core 0", "for core 1", ... + * NB that the memory region size of 0x100 applies for the 11MPCore + * and also cores following the GIC v1 spec (ie A9). + * GIC v2 defines a larger memory region (0x1000) so this will need + * to be extended when we implement A15. + */ + memory_region_init_io(&s->cpuiomem[0], &gic_thiscpu_ops, s, + "gic_cpu", 0x100); + for (i = 0; i < NUM_CPU(s); i++) { + s->backref[i] = s; + memory_region_init_io(&s->cpuiomem[i+1], &gic_cpu_ops, &s->backref[i], + "gic_cpu", 0x100); + } +#endif + gic_reset(s); register_savevm(NULL, "arm_gic", -1, 2, gic_save, gic_load, s); }