From patchwork Mon Oct 10 16:24:05 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 4594 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id ABF7A23DEF for ; Mon, 10 Oct 2011 16:24:12 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 6B1E6A181C9 for ; Mon, 10 Oct 2011 16:24:12 +0000 (UTC) Received: by yxm34 with SMTP id 34so8512129yxm.11 for ; Mon, 10 Oct 2011 09:24:12 -0700 (PDT) Received: by 10.223.85.139 with SMTP id o11mr33301991fal.0.1318263851654; Mon, 10 Oct 2011 09:24:11 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.24.41 with SMTP id r9cs122027laf; Mon, 10 Oct 2011 09:24:11 -0700 (PDT) Received: by 10.204.130.9 with SMTP id q9mr6844993bks.43.1318263850458; Mon, 10 Oct 2011 09:24:10 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id v13si10414835bkd.50.2011.10.10.09.24.09 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 10 Oct 2011 09:24:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1RDIe8-0004Sa-5a; Mon, 10 Oct 2011 17:24:08 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 2/5] target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIV Date: Mon, 10 Oct 2011 17:24:05 +0100 Message-Id: <1318263848-17117-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1318263848-17117-1-git-send-email-peter.maydell@linaro.org> References: <1318263848-17117-1-git-send-email-peter.maydell@linaro.org> Rename the ARM_FEATURE_DIV feature bit to _THUMB_DIV, to make room for a new feature switch enabling DIV in the ARM encoding. (Cores may implement either (a) no divide insns (b) divide insns in Thumb encodings only (c) divide insns in both ARM and Thumb encodings.) Signed-off-by: Peter Maydell --- target-arm/cpu.h | 2 +- target-arm/helper.c | 4 ++-- target-arm/translate.c | 3 ++- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6ab780d..00e012e 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -366,7 +366,7 @@ enum arm_features { ARM_FEATURE_VFP3, ARM_FEATURE_VFP_FP16, ARM_FEATURE_NEON, - ARM_FEATURE_DIV, + ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ ARM_FEATURE_M, /* Microcontroller profile. */ ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ ARM_FEATURE_THUMB2EE, diff --git a/target-arm/helper.c b/target-arm/helper.c index e2428eb..2cf6705 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -193,7 +193,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_V7); set_feature(env, ARM_FEATURE_M); - set_feature(env, ARM_FEATURE_DIV); + set_feature(env, ARM_FEATURE_THUMB_DIV); break; case ARM_CPUID_ANY: /* For userspace emulation. */ set_feature(env, ARM_FEATURE_V4T); @@ -207,7 +207,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) set_feature(env, ARM_FEATURE_VFP_FP16); set_feature(env, ARM_FEATURE_NEON); set_feature(env, ARM_FEATURE_THUMB2EE); - set_feature(env, ARM_FEATURE_DIV); + set_feature(env, ARM_FEATURE_THUMB_DIV); set_feature(env, ARM_FEATURE_V7MP); break; case ARM_CPUID_TI915T: diff --git a/target-arm/translate.c b/target-arm/translate.c index e99fc18..deb0bcf 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -8513,8 +8513,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) tmp2 = load_reg(s, rm); if ((op & 0x50) == 0x10) { /* sdiv, udiv */ - if (!arm_feature(env, ARM_FEATURE_DIV)) + if (!arm_feature(env, ARM_FEATURE_THUMB_DIV)) { goto illegal_op; + } if (op & 0x20) gen_helper_udiv(tmp, tmp, tmp2); else