From patchwork Wed Sep 28 17:27:31 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 4415 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id F1A4123EFA for ; Wed, 28 Sep 2011 17:27:38 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id E722FA1870F for ; Wed, 28 Sep 2011 17:27:38 +0000 (UTC) Received: by mail-fx0-f52.google.com with SMTP id 23so1248729fxe.11 for ; Wed, 28 Sep 2011 10:27:38 -0700 (PDT) Received: by 10.223.94.134 with SMTP id z6mr14676577fam.8.1317230858846; Wed, 28 Sep 2011 10:27:38 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.3.234 with SMTP id f10cs121745laf; Wed, 28 Sep 2011 10:27:38 -0700 (PDT) Received: by 10.227.58.148 with SMTP id g20mr1817896wbh.108.1317230854999; Wed, 28 Sep 2011 10:27:34 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id fi7si24361987wbb.108.2011.09.28.10.27.34 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 28 Sep 2011 10:27:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1R8xuv-0006VH-DW; Wed, 28 Sep 2011 18:27:33 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 3/5] target-arm: Add ARM UDIV/SDIV support Date: Wed, 28 Sep 2011 18:27:31 +0100 Message-Id: <1317230853-24970-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1317230853-24970-1-git-send-email-peter.maydell@linaro.org> References: <1317230853-24970-1-git-send-email-peter.maydell@linaro.org> Add support for UDIV and SDIV in ARM mode. This is a new optional feature for A profile cores (Thumb mode has had UDIV and SDIV for M profile cores for some time). Signed-off-by: Peter Maydell --- target-arm/translate.c | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+), 0 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index e99fc18..d3d7c5c 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7639,6 +7639,25 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) store_reg(s, rn, tmp); } break; + case 1: + case 3: + /* SDIV, UDIV */ + if (!arm_feature(env, ARM_FEATURE_DIV)) { + goto illegal_op; + } + if (((insn >> 5) & 7) || (rd != 15)) { + goto illegal_op; + } + tmp = load_reg(s, rm); + tmp2 = load_reg(s, rs); + if (insn & (1 << 21)) { + gen_helper_udiv(tmp, tmp, tmp2); + } else { + gen_helper_sdiv(tmp, tmp, tmp2); + } + tcg_temp_free_i32(tmp2); + store_reg(s, rn, tmp); + break; default: goto illegal_op; }