From patchwork Wed Sep 14 17:49:00 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 4076 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 50B5F23EFD for ; Wed, 14 Sep 2011 17:49:04 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id 3A454A1891F for ; Wed, 14 Sep 2011 17:49:04 +0000 (UTC) Received: by fxe23 with SMTP id 23so2658640fxe.11 for ; Wed, 14 Sep 2011 10:49:04 -0700 (PDT) Received: by 10.223.5.76 with SMTP id 12mr138318fau.103.1316022544069; Wed, 14 Sep 2011 10:49:04 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.11.8 with SMTP id m8cs59935lab; Wed, 14 Sep 2011 10:49:03 -0700 (PDT) Received: by 10.14.14.34 with SMTP id c34mr38665eec.141.1316022543588; Wed, 14 Sep 2011 10:49:03 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id d51si344601eea.121.2011.09.14.10.49.03 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 14 Sep 2011 10:49:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1R3ta0-0008AE-KH; Wed, 14 Sep 2011 18:49:00 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Gerd Hoffmann Subject: [PATCH 2/2] hw/usb-ohci: Fix OHCI_TD_T1 bit position definition Date: Wed, 14 Sep 2011 18:49:00 +0100 Message-Id: <1316022540-31355-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1316022540-31355-1-git-send-email-peter.maydell@linaro.org> References: <1316022540-31355-1-git-send-email-peter.maydell@linaro.org> The OHCI Transfer Descriptor T (DataToggle) bits are 24 and 25; fix an error which accidentally overlaid them both on the same bit. Signed-off-by: Peter Maydell --- hw/usb-ohci.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c index 7487188..d314743 100644 --- a/hw/usb-ohci.c +++ b/hw/usb-ohci.c @@ -150,7 +150,7 @@ static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev); #define OHCI_TD_DI_SHIFT 21 #define OHCI_TD_DI_MASK (7<