From patchwork Thu Sep 1 17:36:53 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 3847 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 6490923F22 for ; Thu, 1 Sep 2011 17:36:59 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id 4E9B0A18635 for ; Thu, 1 Sep 2011 17:36:59 +0000 (UTC) Received: by fxd18 with SMTP id 18so1310787fxd.11 for ; Thu, 01 Sep 2011 10:36:59 -0700 (PDT) Received: by 10.223.88.214 with SMTP id b22mr169103fam.5.1314898619142; Thu, 01 Sep 2011 10:36:59 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.11.8 with SMTP id m8cs60763lab; Thu, 1 Sep 2011 10:36:59 -0700 (PDT) Received: by 10.213.3.19 with SMTP id 19mr121000ebl.36.1314898616912; Thu, 01 Sep 2011 10:36:56 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk [81.2.115.146]) by mx.google.com with ESMTPS id x2si225554eem.129.2011.09.01.10.36.56 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 01 Sep 2011 10:36:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1QzBCA-0000Xr-1U; Thu, 01 Sep 2011 18:36:54 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Avi Kivity Subject: [PATCH 2/2] hw/versatile_pci: Expose multiple sysbus mmio regions Date: Thu, 1 Sep 2011 18:36:53 +0100 Message-Id: <1314898613-2066-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1314898613-2066-1-git-send-email-peter.maydell@linaro.org> References: <1314898613-2066-1-git-send-email-peter.maydell@linaro.org> Clean up versatile_pci to expose the various PCI mmio regions properly as separate mmio regions rather than as a single mmio which uses callbacks to map and unmap everything. Signed-off-by: Peter Maydell --- hw/realview.c | 12 ++++++++++-- hw/versatile_pci.c | 42 ++++++++---------------------------------- hw/versatilepb.c | 12 ++++++++++-- 3 files changed, 28 insertions(+), 38 deletions(-) diff --git a/hw/realview.c b/hw/realview.c index 549bb15..11ffb8a 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -272,8 +272,16 @@ static void realview_init(ram_addr_t ram_size, sysbus_create_simple("pl031", 0x10017000, pic[10]); if (!is_pb) { - dev = sysbus_create_varargs("realview_pci", 0x60000000, - pic[48], pic[49], pic[50], pic[51], NULL); + dev = qdev_create(NULL, "realview_pci"); + busdev = sysbus_from_qdev(dev); + qdev_init_nofail(dev); + sysbus_mmio_map(busdev, 0, 0x61000000); /* PCI self-config */ + sysbus_mmio_map(busdev, 1, 0x62000000); /* PCI config */ + sysbus_mmio_map(busdev, 2, 0x63000000); /* PCI I/O */ + sysbus_connect_irq(busdev, 0, pic[48]); + sysbus_connect_irq(busdev, 1, pic[49]); + sysbus_connect_irq(busdev, 2, pic[50]); + sysbus_connect_irq(busdev, 3, pic[51]); pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); if (usb_enabled) { usb_ohci_init_pci(pci_bus, -1); diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c index 98e56f1..8a88696 100644 --- a/hw/versatile_pci.c +++ b/hw/versatile_pci.c @@ -58,38 +58,6 @@ static void pci_vpb_set_irq(void *opaque, int irq_num, int level) qemu_set_irq(pic[irq_num], level); } - -static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base) -{ - PCIVPBState *s = (PCIVPBState *)dev; - /* Selfconfig area. */ - memory_region_add_subregion(get_system_memory(), base + 0x01000000, - &s->mem_config); - /* Normal config area. */ - memory_region_add_subregion(get_system_memory(), base + 0x02000000, - &s->mem_config2); - - if (s->realview) { - /* IO memory area. */ - memory_region_add_subregion(get_system_memory(), base + 0x03000000, - &s->isa); - } -} - -static void pci_vpb_unmap(SysBusDevice *dev, target_phys_addr_t base) -{ - PCIVPBState *s = (PCIVPBState *)dev; - /* Selfconfig area. */ - memory_region_del_subregion(get_system_memory(), &s->mem_config); - /* Normal config area. */ - memory_region_del_subregion(get_system_memory(), &s->mem_config2); - - if (s->realview) { - /* IO memory area. */ - memory_region_del_subregion(get_system_memory(), &s->isa); - } -} - static int pci_vpb_init(SysBusDevice *dev) { PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev); @@ -106,16 +74,22 @@ static int pci_vpb_init(SysBusDevice *dev) /* ??? Register memory space. */ + /* Our memory regions are: + * 0 : PCI self config window + * 1 : PCI config window + * 2 : PCI IO window (realview_pci only) + */ memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, bus, "pci-vpb-selfconfig", 0x1000000); + sysbus_init_mmio_region(dev, &s->mem_config); memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, bus, "pci-vpb-config", 0x1000000); + sysbus_init_mmio_region(dev, &s->mem_config2); if (s->realview) { isa_mmio_setup(&s->isa, 0x0100000); + sysbus_init_mmio_region(dev, &s->isa); } - sysbus_init_mmio_cb2(dev, pci_vpb_map, pci_vpb_unmap); - pci_create_simple(bus, -1, "versatile_pci_host"); return 0; } diff --git a/hw/versatilepb.c b/hw/versatilepb.c index 49f8f5f..68402cc 100644 --- a/hw/versatilepb.c +++ b/hw/versatilepb.c @@ -181,6 +181,7 @@ static void versatile_init(ram_addr_t ram_size, qemu_irq pic[32]; qemu_irq sic[32]; DeviceState *dev, *sysctl; + SysBusDevice *busdev; PCIBus *pci_bus; NICInfo *nd; int n; @@ -219,8 +220,15 @@ static void versatile_init(ram_addr_t ram_size, sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); - dev = sysbus_create_varargs("versatile_pci", 0x40000000, - sic[27], sic[28], sic[29], sic[30], NULL); + dev = qdev_create(NULL, "versatile_pci"); + busdev = sysbus_from_qdev(dev); + qdev_init_nofail(dev); + sysbus_mmio_map(busdev, 0, 0x41000000); /* PCI self-config */ + sysbus_mmio_map(busdev, 1, 0x42000000); /* PCI config */ + sysbus_connect_irq(busdev, 0, sic[27]); + sysbus_connect_irq(busdev, 1, sic[28]); + sysbus_connect_irq(busdev, 2, sic[29]); + sysbus_connect_irq(busdev, 3, sic[30]); pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); /* The Versatile PCI bridge does not provide access to PCI IO space,