From patchwork Fri Jul 15 14:58:15 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2717 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 1931323F42 for ; Fri, 15 Jul 2011 14:58:36 +0000 (UTC) Received: from mail-qw0-f52.google.com (mail-qw0-f52.google.com [209.85.216.52]) by fiordland.canonical.com (Postfix) with ESMTP id BFB3CA18709 for ; Fri, 15 Jul 2011 14:58:35 +0000 (UTC) Received: by qwb8 with SMTP id 8so904513qwb.11 for ; Fri, 15 Jul 2011 07:58:35 -0700 (PDT) Received: by 10.229.25.212 with SMTP id a20mr2757039qcc.148.1310741915123; Fri, 15 Jul 2011 07:58:35 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.229.217.78 with SMTP id hl14cs50437qcb; Fri, 15 Jul 2011 07:58:34 -0700 (PDT) Received: by 10.213.28.146 with SMTP id m18mr266661ebc.47.1310741911863; Fri, 15 Jul 2011 07:58:31 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk [81.2.115.146]) by mx.google.com with ESMTPS id d46si831992eei.44.2011.07.15.07.58.31 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 15 Jul 2011 07:58:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1QhjqU-0000QN-Az; Fri, 15 Jul 2011 15:58:26 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Riku Voipio , =?UTF-8?q?Juha=20Riihim=C3=A4ki?= , andrzej zaborowski , Markus Armbruster Subject: [PATCH 01/12] hw/nand: Pass block device state to init function Date: Fri, 15 Jul 2011 15:58:15 +0100 Message-Id: <1310741906-1606-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1310741906-1606-1-git-send-email-peter.maydell@linaro.org> References: <1310741906-1606-1-git-send-email-peter.maydell@linaro.org> Pass the BlockDeviceState to the nand_init() function rather than having it look it up via drive_get() itself. Signed-off-by: Peter Maydell --- hw/axis_dev88.c | 6 +++++- hw/flash.h | 2 +- hw/nand.c | 8 ++------ hw/spitz.c | 4 +++- hw/tc6393xb.c | 5 ++++- 5 files changed, 15 insertions(+), 10 deletions(-) diff --git a/hw/axis_dev88.c b/hw/axis_dev88.c index 0e2135a..de1f5a5 100644 --- a/hw/axis_dev88.c +++ b/hw/axis_dev88.c @@ -30,6 +30,7 @@ #include "loader.h" #include "elf.h" #include "cris-boot.h" +#include "blockdev.h" #define D(x) #define DNAND(x) @@ -251,6 +252,7 @@ void axisdev88_init (ram_addr_t ram_size, CPUState *env; DeviceState *dev; SysBusDevice *s; + DriveInfo *nand; qemu_irq irq[30], nmi[2], *cpu_irq; void *etraxfs_dmac; struct etraxfs_dma_client *eth[2] = {NULL, NULL}; @@ -278,7 +280,9 @@ void axisdev88_init (ram_addr_t ram_size, /* Attach a NAND flash to CS1. */ - nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39); + nand = drive_get(IF_MTD, 0, 0); + nand_state.nand = nand_init(nand ? nand->bdrv : NULL, + NAND_MFR_STMICRO, 0x39); nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs); diff --git a/hw/flash.h b/hw/flash.h index c22e1a9..a992bb8 100644 --- a/hw/flash.h +++ b/hw/flash.h @@ -19,7 +19,7 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, /* nand.c */ typedef struct NANDFlashState NANDFlashState; -NANDFlashState *nand_init(int manf_id, int chip_id); +NANDFlashState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id); void nand_done(NANDFlashState *s); void nand_setpins(NANDFlashState *s, uint8_t cle, uint8_t ale, uint8_t ce, uint8_t wp, uint8_t gnd); diff --git a/hw/nand.c b/hw/nand.c index 37e51d7..d6204d9 100644 --- a/hw/nand.c +++ b/hw/nand.c @@ -14,7 +14,6 @@ # include "hw.h" # include "flash.h" # include "blockdev.h" -/* FIXME: Pass block device as an argument. */ # define NAND_CMD_READ0 0x00 # define NAND_CMD_READ1 0x01 @@ -451,20 +450,17 @@ uint8_t nand_getio(NANDFlashState *s) return *(s->ioaddr ++); } -NANDFlashState *nand_init(int manf_id, int chip_id) +NANDFlashState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id) { int pagesize; NANDFlashState *s; - DriveInfo *dinfo; if (nand_flash_ids[chip_id].size == 0) { hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__); } s = (NANDFlashState *) qemu_mallocz(sizeof(NANDFlashState)); - dinfo = drive_get(IF_MTD, 0, 0); - if (dinfo) - s->bdrv = dinfo->bdrv; + s->bdrv = bdrv; s->manf_id = manf_id; s->chip_id = chip_id; s->size = nand_flash_ids[s->chip_id].size << 20; diff --git a/hw/spitz.c b/hw/spitz.c index 006f7a9..78e9c34 100644 --- a/hw/spitz.c +++ b/hw/spitz.c @@ -169,11 +169,13 @@ static void sl_flash_register(PXA2xxState *cpu, int size) static int sl_nand_init(SysBusDevice *dev) { int iomemtype; SLNANDState *s; + DriveInfo *nand; s = FROM_SYSBUS(SLNANDState, dev); s->ctl = 0; - s->nand = nand_init(s->manf_id, s->chip_id); + nand = drive_get(IF_MTD, 0, 0); + s->nand = nand_init(nand ? nand->bdrv : NULL, s->manf_id, s->chip_id); iomemtype = cpu_register_io_memory(sl_readfn, sl_writefn, s, DEVICE_NATIVE_ENDIAN); diff --git a/hw/tc6393xb.c b/hw/tc6393xb.c index ed49e94..4de0819 100644 --- a/hw/tc6393xb.c +++ b/hw/tc6393xb.c @@ -12,6 +12,7 @@ #include "flash.h" #include "console.h" #include "pixel_ops.h" +#include "blockdev.h" #define IRQ_TC6393_NAND 0 #define IRQ_TC6393_MMC 1 @@ -566,6 +567,7 @@ TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq) { int iomemtype; TC6393xbState *s; + DriveInfo *nand; CPUReadMemoryFunc * const tc6393xb_readfn[] = { tc6393xb_readb, tc6393xb_readw, @@ -586,7 +588,8 @@ TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq) s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS); - s->flash = nand_init(NAND_MFR_TOSHIBA, 0x76); + nand = drive_get(IF_MTD, 0, 0); + s->flash = nand_init(nand ? nand->bdrv : NULL, NAND_MFR_TOSHIBA, 0x76); iomemtype = cpu_register_io_memory(tc6393xb_readfn, tc6393xb_writefn, s, DEVICE_NATIVE_ENDIAN);