From patchwork Tue May 31 16:48:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1681 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:54:21 -0000 Delivered-To: patches@linaro.org Received: by 10.52.110.9 with SMTP id hw9cs301313vdb; Tue, 31 May 2011 09:48:27 -0700 (PDT) Received: by 10.216.53.203 with SMTP id g53mr6165844wec.13.1306860506106; Tue, 31 May 2011 09:48:26 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk [81.2.115.146]) by mx.google.com with ESMTPS id y60si587240wec.56.2011.05.31.09.48.25 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 31 May 2011 09:48:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1QRS7D-0003S7-Sr; Tue, 31 May 2011 17:48:23 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH] smc91c111: qdevify reset Date: Tue, 31 May 2011 17:48:23 +0100 Message-Id: <1306860503-13248-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 MIME-Version: 1.0 From: Juha Riihimäki Register the smc91c111 reset function as a qdev reset function. Signed-off-by: Juha Riihimäki Reviewed-by: Peter Maydell --- hw/smc91c111.c | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-) diff --git a/hw/smc91c111.c b/hw/smc91c111.c index dafea5c..701baaf 100644 --- a/hw/smc91c111.c +++ b/hw/smc91c111.c @@ -252,8 +252,9 @@ static void smc91c111_queue_tx(smc91c111_state *s, int packet) smc91c111_do_tx(s); } -static void smc91c111_reset(smc91c111_state *s) +static void smc91c111_reset(DeviceState *dev) { + smc91c111_state *s = FROM_SYSBUS(smc91c111_state, sysbus_from_qdev(dev)); s->bank = 0; s->tx_fifo_len = 0; s->tx_fifo_done_len = 0; @@ -302,7 +303,7 @@ static void smc91c111_writeb(void *opaque, target_phys_addr_t offset, case 5: SET_HIGH(rcr, value); if (s->rcr & RCR_SOFT_RST) - smc91c111_reset(s); + smc91c111_reset(&s->busdev.qdev); return; case 10: case 11: /* RPCR */ /* Ignored */ @@ -753,9 +754,6 @@ static int smc91c111_init1(SysBusDevice *dev) sysbus_init_mmio(dev, 16, s->mmio_index); sysbus_init_irq(dev, &s->irq); qemu_macaddr_default_if_unset(&s->conf.macaddr); - - smc91c111_reset(s); - s->nic = qemu_new_nic(&net_smc91c111_info, &s->conf, dev->qdev.info->name, dev->qdev.id, s); qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); @@ -768,6 +766,7 @@ static SysBusDeviceInfo smc91c111_info = { .qdev.name = "smc91c111", .qdev.size = sizeof(smc91c111_state), .qdev.vmsd = &vmstate_smc91c111, + .qdev.reset = smc91c111_reset, .qdev.props = (Property[]) { DEFINE_NIC_PROPERTIES(smc91c111_state, conf), DEFINE_PROP_END_OF_LIST(),