From patchwork Thu May 26 16:34:11 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1647 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:53:47 -0000 Delivered-To: patches@linaro.org Received: by 10.52.181.230 with SMTP id dz6cs34450vdc; Thu, 26 May 2011 09:34:14 -0700 (PDT) Received: by 10.216.241.78 with SMTP id f56mr993574wer.76.1306427653849; Thu, 26 May 2011 09:34:13 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk [81.2.115.146]) by mx.google.com with ESMTPS id f66si1736058wef.31.2011.05.26.09.34.13 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 26 May 2011 09:34:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1QPdVj-0000ve-KT; Thu, 26 May 2011 17:34:11 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH] hw/9118.c: Implement active-low interrupt support Date: Thu, 26 May 2011 17:34:11 +0100 Message-Id: <1306427651-3547-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 The 9118 ethernet controller interrupt line is active low unless the IRQ config register is programmed to set both the IRQ_POL (polarity: active-high) and IRQ_TYPE (type: push-pull) bits: implement support for inverting the irq output in other configurations. This also requires that we support setting the bits in the first place, and that we correctly preserve them across software reset. Signed-off-by: Peter Maydell --- The motivation for this patch is actually an omap3 platform (overo) which uses the active-low configuration; the platforms in QEMU mainline which use it (vexpress and realview) both configure the chip to active-high, which is why this bug hasn't come to light before. I've tested that (a) my overo platform works with the change and (b) it doesn't regress vexpress. hw/lan9118.c | 12 +++++++++--- 1 files changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/lan9118.c b/hw/lan9118.c index 4c42fe9..3f3c05d 100644 --- a/hw/lan9118.c +++ b/hw/lan9118.c @@ -228,6 +228,12 @@ static void lan9118_update(lan9118_state *s) if ((s->irq_cfg & IRQ_EN) == 0) { level = 0; } + if ((s->irq_cfg & (IRQ_TYPE | IRQ_POL)) != (IRQ_TYPE | IRQ_POL)) { + /* Interrupt is active low unless we're configured as + * active-high polarity, push-pull type. + */ + level = !level; + } qemu_set_irq(s->irq, level); } @@ -294,8 +300,7 @@ static void phy_reset(lan9118_state *s) static void lan9118_reset(DeviceState *d) { lan9118_state *s = FROM_SYSBUS(lan9118_state, sysbus_from_qdev(d)); - - s->irq_cfg &= ~(IRQ_TYPE | IRQ_POL); + s->irq_cfg &= (IRQ_TYPE | IRQ_POL); s->int_sts = 0; s->int_en = 0; s->fifo_int = 0x48000000; @@ -904,7 +909,8 @@ static void lan9118_writel(void *opaque, target_phys_addr_t offset, switch (offset) { case CSR_IRQ_CFG: /* TODO: Implement interrupt deassertion intervals. */ - s->irq_cfg = (s->irq_cfg & IRQ_INT) | (val & IRQ_EN); + val &= (IRQ_EN | IRQ_POL | IRQ_TYPE); + s->irq_cfg = (s->irq_cfg & IRQ_INT) | val; break; case CSR_INT_STS: s->int_sts &= ~val;