From patchwork Tue Apr 26 17:17:20 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1181 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:49:58 -0000 Delivered-To: patches@linaro.org Received: by 10.224.2.73 with SMTP id 9cs78992qai; Tue, 26 Apr 2011 10:17:26 -0700 (PDT) Received: by 10.216.62.131 with SMTP id y3mr914769wec.71.1303838245240; Tue, 26 Apr 2011 10:17:25 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk [81.2.115.146]) by mx.google.com with ESMTPS id t11si15603607wes.207.2011.04.26.10.17.24 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 26 Apr 2011 10:17:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1QElt2-0003XV-4s; Tue, 26 Apr 2011 18:17:20 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: YuYeon Oh , patches@linaro.org Subject: [PATCH] target-arm: Don't update base register on abort in Thumb T1 LDM Date: Tue, 26 Apr 2011 18:17:20 +0100 Message-Id: <1303838240-13582-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 Make sure the base register isn't updated if it is in the load list for a Thumb LDM (T1 encoding) which aborts partway through the load. Signed-off-by: Peter Maydell --- target-arm/translate.c | 17 ++++++++++++++--- 1 files changed, 14 insertions(+), 3 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index d8da514..a1af436 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -9454,7 +9454,10 @@ static void disas_thumb_insn(CPUState *env, DisasContext *s) break; case 12: + { /* load/store multiple */ + TCGv loaded_var; + TCGV_UNUSED(loaded_var); rn = (insn >> 8) & 0x7; addr = load_reg(s, rn); for (i = 0; i < 8; i++) { @@ -9462,7 +9465,11 @@ static void disas_thumb_insn(CPUState *env, DisasContext *s) if (insn & (1 << 11)) { /* load */ tmp = gen_ld32(addr, IS_USER(s)); - store_reg(s, i, tmp); + if (i == rn) { + loaded_var = tmp; + } else { + store_reg(s, i, tmp); + } } else { /* store */ tmp = load_reg(s, i); @@ -9472,14 +9479,18 @@ static void disas_thumb_insn(CPUState *env, DisasContext *s) tcg_gen_addi_i32(addr, addr, 4); } } - /* Base register writeback. */ if ((insn & (1 << rn)) == 0) { + /* base reg not in list: base register writeback */ store_reg(s, rn, addr); } else { + /* base reg in list: if load, complete it now */ + if (insn & (1 << 11)) { + store_reg(s, rn, loaded_var); + } tcg_temp_free_i32(addr); } break; - + } case 13: /* conditional branch or swi */ cond = (insn >> 8) & 0xf;