From patchwork Mon Mar 14 15:37:12 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 556 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:43:40 -0000 Delivered-To: patches@linaro.org Received: by 10.224.45.75 with SMTP id d11cs59371qaf; Mon, 14 Mar 2011 08:37:16 -0700 (PDT) Received: by 10.227.39.66 with SMTP id f2mr2836091wbe.2.1300117035960; Mon, 14 Mar 2011 08:37:15 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk [81.2.115.146]) by mx.google.com with ESMTPS id l2si14047579wba.28.2011.03.14.08.37.15 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 14 Mar 2011 08:37:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1Pz9pZ-00073t-Ni; Mon, 14 Mar 2011 15:37:13 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 1/2] target-arm: Fix VRECPS edge cases handling Date: Mon, 14 Mar 2011 15:37:12 +0000 Message-Id: <1300117033-27120-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1300117033-27120-1-git-send-email-peter.maydell@linaro.org> References: <1300117033-27120-1-git-send-email-peter.maydell@linaro.org> Correct the handling of edge cases for the VRECPS instruction: * this is a Neon instruction so uses the "standard FPSCR value" * (zero, inf) is a special case which returns 2.0 Signed-off-by: Peter Maydell --- target-arm/helper.c | 11 ++++++++--- 1 files changed, 8 insertions(+), 3 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index d360121..c01a5a2 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2707,11 +2707,16 @@ uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env) return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); } +#define float32_two make_float32(0x40000000) + float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env) { - float_status *s = &env->vfp.fp_status; - float32 two = int32_to_float32(2, s); - return float32_sub(two, float32_mul(a, b, s), s); + float_status *s = &env->vfp.standard_fp_status; + if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || + (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { + return float32_two; + } + return float32_sub(float32_two, float32_mul(a, b, s), s); } float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)