From patchwork Fri Mar 11 18:12:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 509 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:43:13 -0000 Delivered-To: patches@linaro.org Received: by 10.224.67.207 with SMTP id s15cs69388qai; Fri, 11 Mar 2011 10:12:30 -0800 (PST) Received: by 10.236.63.241 with SMTP id a77mr3277798yhd.163.1299867150752; Fri, 11 Mar 2011 10:12:30 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk [81.2.115.146]) by mx.google.com with ESMTPS id 49si11211609yhl.69.2011.03.11.10.12.28 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 11 Mar 2011 10:12:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1Py6p9-0005kC-1f; Fri, 11 Mar 2011 18:12:27 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 4/7] target-arm: Fix VCLE.F32 #0, VCLT.F32 #0 NaN handling Date: Fri, 11 Mar 2011 18:12:23 +0000 Message-Id: <1299867146-22049-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299867146-22049-1-git-send-email-peter.maydell@linaro.org> References: <1299867146-22049-1-git-send-email-peter.maydell@linaro.org> Implementing the floating-point versions of VCLE #0 and VCLT #0 by doing a GT comparison and inverting the result gives the wrong result if the input is a NaN. Implement as a GT comparison with the operands swapped instead. Signed-off-by: Peter Maydell --- target-arm/translate.c | 18 ++++++++++++------ 1 files changed, 12 insertions(+), 6 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index f4be8dc..adba4bf 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -5639,25 +5639,31 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) gen_neon_rsb(size, tmp, tmp2); tcg_temp_free(tmp2); break; - case 24: case 27: /* Float VCGT #0, Float VCLE #0 */ + case 24: /* Float VCGT #0 */ tmp2 = tcg_const_i32(0); gen_helper_neon_cgt_f32(tmp, cpu_env, tmp, tmp2); tcg_temp_free(tmp2); - if (op == 27) - tcg_gen_not_i32(tmp, tmp); break; - case 25: case 28: /* Float VCGE #0, Float VCLT #0 */ + case 25: /* Float VCGE #0 */ tmp2 = tcg_const_i32(0); gen_helper_neon_cge_f32(tmp, cpu_env, tmp, tmp2); tcg_temp_free(tmp2); - if (op == 28) - tcg_gen_not_i32(tmp, tmp); break; case 26: /* Float VCEQ #0 */ tmp2 = tcg_const_i32(0); gen_helper_neon_ceq_f32(tmp, cpu_env, tmp, tmp2); tcg_temp_free(tmp2); break; + case 27: /* Float VCLE #0 */ + tmp2 = tcg_const_i32(0); + gen_helper_neon_cge_f32(tmp, cpu_env, tmp2, tmp); + tcg_temp_free(tmp2); + break; + case 28: /* Float VCLT #0 */ + tmp2 = tcg_const_i32(0); + gen_helper_neon_cgt_f32(tmp, cpu_env, tmp2, tmp); + tcg_temp_free(tmp2); + break; case 30: /* Float VABS */ gen_vfp_abs(0); break;