From patchwork Thu Mar 10 16:48:49 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 492 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:43:06 -0000 Delivered-To: patches@linaro.org Received: by 10.224.67.207 with SMTP id s15cs26207qai; Thu, 10 Mar 2011 08:48:54 -0800 (PST) Received: by 10.227.131.195 with SMTP id y3mr7280212wbs.38.1299775733880; Thu, 10 Mar 2011 08:48:53 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk [81.2.115.146]) by mx.google.com with ESMTPS id z66si6021561weq.192.2011.03.10.08.48.52 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 10 Mar 2011 08:48:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1Pxj2f-0005AQ-UD; Thu, 10 Mar 2011 16:48:49 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH] target-arm: Fix UNDEF cases in Thumb load/store Date: Thu, 10 Mar 2011 16:48:49 +0000 Message-Id: <1299775729-19839-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.3 Decode of Thumb load/store was merging together the cases of 'bit 11==0' (reg+reg LSL imm) and 'bit 11==1' (reg+imm). This happens to work for valid instruction patterns but meant that we would not UNDEF for the cases the architecture mandates that we must. Make the decode actually look at bit 11 as well as [10..8] so that we UNDEF in the right places. This change also removes what was a spurious unreachable 'case 8', and correctly frees TCG temporaries on the illegal-insn codepaths. Signed-off-by: Peter Maydell --- This patch was mostly prompted by that dodgy 'case 8' which I noted when doing the preload/hint space patches a month or so ago; I have finally added support for testing loads and stores to risu, so I can confirm that this patch doesn't break the non-UNDEF cases. target-arm/translate.c | 29 ++++++++++++++++++----------- 1 files changed, 18 insertions(+), 11 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 062de5e..0afdbfb 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -8378,39 +8378,42 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) tcg_gen_addi_i32(addr, addr, imm); } else { imm = insn & 0xff; - switch ((insn >> 8) & 7) { - case 0: case 8: /* Shifted Register. */ + switch ((insn >> 8) & 0xf) { + case 0x0: /* Shifted Register. */ shift = (insn >> 4) & 0xf; - if (shift > 3) + if (shift > 3) { + tcg_temp_free_i32(addr); goto illegal_op; + } tmp = load_reg(s, rm); if (shift) tcg_gen_shli_i32(tmp, tmp, shift); tcg_gen_add_i32(addr, addr, tmp); tcg_temp_free_i32(tmp); break; - case 4: /* Negative offset. */ + case 0xc: /* Negative offset. */ tcg_gen_addi_i32(addr, addr, -imm); break; - case 6: /* User privilege. */ + case 0xe: /* User privilege. */ tcg_gen_addi_i32(addr, addr, imm); user = 1; break; - case 1: /* Post-decrement. */ + case 0x9: /* Post-decrement. */ imm = -imm; /* Fall through. */ - case 3: /* Post-increment. */ + case 0xb: /* Post-increment. */ postinc = 1; writeback = 1; break; - case 5: /* Pre-decrement. */ + case 0xd: /* Pre-decrement. */ imm = -imm; /* Fall through. */ - case 7: /* Pre-increment. */ + case 0xf: /* Pre-increment. */ tcg_gen_addi_i32(addr, addr, imm); writeback = 1; break; default: + tcg_temp_free_i32(addr); goto illegal_op; } } @@ -8423,7 +8426,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) case 1: tmp = gen_ld16u(addr, user); break; case 5: tmp = gen_ld16s(addr, user); break; case 2: tmp = gen_ld32(addr, user); break; - default: goto illegal_op; + default: + tcg_temp_free_i32(addr); + goto illegal_op; } if (rs == 15) { gen_bx(s, tmp); @@ -8437,7 +8442,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) case 0: gen_st8(tmp, addr, user); break; case 1: gen_st16(tmp, addr, user); break; case 2: gen_st32(tmp, addr, user); break; - default: goto illegal_op; + default: + tcg_temp_free_i32(addr); + goto illegal_op; } } if (postinc)