From patchwork Tue Feb 22 18:19:43 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 197 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:40:48 -0000 Delivered-To: patches@linaro.org Received: by 10.224.19.208 with SMTP id c16cs251734qab; Tue, 22 Feb 2011 10:19:47 -0800 (PST) Received: by 10.14.45.75 with SMTP id o51mr3331456eeb.49.1298398786886; Tue, 22 Feb 2011 10:19:46 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk [81.2.115.146]) by mx.google.com with ESMTPS id s42si17076223eeh.41.2011.02.22.10.19.45 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 22 Feb 2011 10:19:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1Prwpr-0004tC-70; Tue, 22 Feb 2011 18:19:43 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH] target-arm: Implement a minimal set of cp14 debug registers Date: Tue, 22 Feb 2011 18:19:43 +0000 Message-Id: <1298398783-18771-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.3 Newer ARM kernels try to probe for whether the CPU has hardware breakpoint support. For this to work QEMU has to implement a minimal set of the cp14 debug registers. The architecture requires v7 cores to implement debug and so there is no defined way to report its absence; however in practice returning a zero DBGDIDR (ie with a reserved value for "debug architecture version") should cause well-written hw debug users to do the right thing. We also implement DBGDRAR and DBGDSAR as RAZ, indicating no memory mapped debug components. Signed-off-by: Peter Maydell --- target-arm/translate.c | 28 ++++++++++++++++++++++++++++ 1 files changed, 28 insertions(+), 0 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index dbd958b..d05859d 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -5769,6 +5769,34 @@ static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn) int rt = (insn >> 12) & 0xf; TCGv tmp; + /* Minimal set of debug registers, since we don't support debug */ + if (op1 == 0 && crn == 0 && op2 == 0) { + switch (crm) { + case 0: + /* DBGDIDR: just RAZ. In particular this means the + * "debug architecture version" bits will read as + * a reserved value, which should cause Linux to + * not try to use the debug hardware. + */ + tmp = tcg_const_i32(0); + store_reg(s, rt, tmp); + return 0; + case 1: + case 2: + /* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we + * don't implement memory mapped debug components + */ + if (ENABLE_ARCH_7) { + tmp = tcg_const_i32(0); + store_reg(s, rt, tmp); + return 0; + } + break; + default: + break; + } + } + if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) { /* TEECR */