From patchwork Mon Feb 21 10:40:17 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:40:39 -0000 Delivered-To: patches@linaro.org Received: by 10.146.25.23 with SMTP id 23cs193385yay; Mon, 21 Feb 2011 02:40:22 -0800 (PST) Received: by 10.204.152.22 with SMTP id e22mr1124329bkw.103.1298284821062; Mon, 21 Feb 2011 02:40:21 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk [81.2.115.146]) by mx.google.com with ESMTPS id j21si5166454faa.114.2011.02.21.02.40.20 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 21 Feb 2011 02:40:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1PrTBi-0004If-Hr; Mon, 21 Feb 2011 10:40:18 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 1/2] target-arm: Refactor to pull narrowing decode into separate function Date: Mon, 21 Feb 2011 10:40:17 +0000 Message-Id: <1298284818-16504-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298284818-16504-1-git-send-email-peter.maydell@linaro.org> References: <1298284818-16504-1-git-send-email-peter.maydell@linaro.org> Pull the code which decodes narrowing operations as being either signed/unsigned saturate or plain out into its own function. Signed-off-by: Peter Maydell --- target-arm/translate.c | 45 +++++++++++++++++++-------------------------- 1 files changed, 19 insertions(+), 26 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 5f377a4..fa20e84 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4164,6 +4164,23 @@ static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u) } } +static void gen_neon_narrow_op(int op, int u, int size, TCGv dest, TCGv_i64 src) +{ + if (op) { + if (u) { + gen_neon_unarrow_sats(size, dest, src); + } else { + gen_neon_narrow(size, dest, src); + } + } else { + if (u) { + gen_neon_narrow_satu(size, dest, src); + } else { + gen_neon_narrow_sats(size, dest, src); + } + } +} + /* Translate a NEON data processing instruction. Return nonzero if the instruction is invalid. We process data in a mixture of 32-bit and 64-bit chunks. @@ -4839,19 +4856,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) dead_tmp(tmp3); } tmp = new_tmp(); - if (op == 8) { - if (u) { /* VQSHRUN / VQRSHRUN */ - gen_neon_unarrow_sats(size - 1, tmp, cpu_V0); - } else { /* VSHRN / VRSHRN */ - gen_neon_narrow(size - 1, tmp, cpu_V0); - } - } else { - if (u) { /* VQSHRN / VQRSHRN */ - gen_neon_narrow_satu(size - 1, tmp, cpu_V0); - } else { /* VQSHRN / VQRSHRN */ - gen_neon_narrow_sats(size - 1, tmp, cpu_V0); - } - } + gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0); neon_store_reg(rd, pass, tmp); } /* for pass */ if (size == 3) { @@ -5439,19 +5444,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) for (pass = 0; pass < 2; pass++) { neon_load_reg64(cpu_V0, rm + pass); tmp = new_tmp(); - if (op == 36) { - if (q) { /* VQMOVUN */ - gen_neon_unarrow_sats(size, tmp, cpu_V0); - } else { /* VMOVN */ - gen_neon_narrow(size, tmp, cpu_V0); - } - } else { /* VQMOVN */ - if (q) { - gen_neon_narrow_satu(size, tmp, cpu_V0); - } else { - gen_neon_narrow_sats(size, tmp, cpu_V0); - } - } + gen_neon_narrow_op(op == 36, q, size, tmp, cpu_V0); if (pass == 0) { tmp2 = tmp; } else {