From patchwork Wed Feb 9 16:27:29 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 98 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:39:57 -0000 Delivered-To: patches@linaro.org Received: by 10.147.124.5 with SMTP id b5cs149916yan; Wed, 9 Feb 2011 08:27:34 -0800 (PST) Received: by 10.90.74.14 with SMTP id w14mr1603202aga.34.1297268854253; Wed, 09 Feb 2011 08:27:34 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk [81.2.115.146]) by mx.google.com with ESMTPS id t5si1158708ano.139.2011.02.09.08.27.33 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 09 Feb 2011 08:27:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1PnCt8-0001Vk-ID; Wed, 09 Feb 2011 16:27:30 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Christophe Lyon Subject: [PATCH v2 5/6] target-arm: Silence NaNs resulting from half-precision conversions Date: Wed, 9 Feb 2011 16:27:29 +0000 Message-Id: <1297268850-5777-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1297268850-5777-1-git-send-email-peter.maydell@linaro.org> References: <1297268850-5777-1-git-send-email-peter.maydell@linaro.org> Silence the NaNs that may result from half-precision conversion, as we do for the other conversions. Signed-off-by: Peter Maydell Reviewed-by: Aurelien Jarno --- target-arm/helper.c | 12 ++++++++++-- 1 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index d46defc..503278c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2627,14 +2627,22 @@ float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env) { float_status *s = &env->vfp.fp_status; int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; - return float16_to_float32(a, ieee, s); + float32 r = float16_to_float32(a, ieee, s); + if (ieee) { + return float32_maybe_silence_nan(r); + } + return r; } uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env) { float_status *s = &env->vfp.fp_status; int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; - return float32_to_float16(a, ieee, s); + float16 r = float32_to_float16(a, ieee, s); + if (ieee) { + return float16_maybe_silence_nan(r); + } + return r; } float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)