From patchwork Thu Feb 3 19:43:22 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 70 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:39:40 -0000 Delivered-To: patches@linaro.org Received: by 10.147.124.5 with SMTP id b5cs60781yan; Thu, 3 Feb 2011 11:43:28 -0800 (PST) Received: by 10.227.146.135 with SMTP id h7mr4023220wbv.111.1296762207197; Thu, 03 Feb 2011 11:43:27 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk [81.2.115.146]) by mx.google.com with ESMTPS id e5si2177438wbi.91.2011.02.03.11.43.26 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 03 Feb 2011 11:43:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1Pl55R-0000nX-3u; Thu, 03 Feb 2011 19:43:25 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 1/4] target-arm: Add CPU feature flag for v7MP Date: Thu, 3 Feb 2011 19:43:22 +0000 Message-Id: <1296762205-3043-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1296762205-3043-1-git-send-email-peter.maydell@linaro.org> References: <1296762205-3043-1-git-send-email-peter.maydell@linaro.org> Add a CPU feature flag for v7MP (the multiprocessing extensions); some instructions exist only for v7MP and not for the base v7 architecture. Signed-off-by: Peter Maydell --- target-arm/cpu.h | 3 ++- target-arm/helper.c | 6 ++++++ 2 files changed, 8 insertions(+), 1 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 5bcd53a..0d96325 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -362,7 +362,8 @@ enum arm_features { ARM_FEATURE_DIV, ARM_FEATURE_M, /* Microcontroller profile. */ ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ - ARM_FEATURE_THUMB2EE + ARM_FEATURE_THUMB2EE, + ARM_FEATURE_V7MP /* v7 Multiprocessing Extensions */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target-arm/helper.c b/target-arm/helper.c index b562767..3cf9181 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -123,6 +123,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) set_feature(env, ARM_FEATURE_VFP_FP16); set_feature(env, ARM_FEATURE_NEON); set_feature(env, ARM_FEATURE_THUMB2EE); + /* Note that A9 supports the MP extensions even for + * A9UP and single-core A9MP (which are both different + * and valid configurations; we don't model A9UP). + */ + set_feature(env, ARM_FEATURE_V7MP); env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */ env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111; @@ -152,6 +157,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) set_feature(env, ARM_FEATURE_NEON); set_feature(env, ARM_FEATURE_THUMB2EE); set_feature(env, ARM_FEATURE_DIV); + set_feature(env, ARM_FEATURE_V7MP); break; case ARM_CPUID_TI915T: case ARM_CPUID_TI925T: