diff mbox series

[v2,13/17] target/riscv: Only support a single VSXL length

Message ID 088e016b3f96a9508165ab3d10217041e8a3e536.1591319882.git.alistair@alistair23.me
State New
Headers show
Series RISC-V: Update the Hypervisor spec to v0.6.1 | expand

Commit Message

Alistair Francis June 5, 2020, 1:21 a.m. UTC 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 9 +++++++++
 1 file changed, 9 insertions(+)
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Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 69a3c8379c..973404d0aa 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -768,12 +768,21 @@  static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
 static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->hstatus;
+#ifdef TARGET_RISCV64
+    /* We only support 64-bit VSXL */
+    *val = set_field(*val, HSTATUS_VSXL, 2);
+#endif
     return 0;
 }
 
 static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
 {
     env->hstatus = val;
+#ifdef TARGET_RISCV64
+    if (get_field(val, HSTATUS_VSXL) != 2) {
+        qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
+    }
+#endif
     return 0;
 }