Show patches with: Series = target/riscv: Rationalize XLEN and operand length       |    Archived = No       |   16 patches
Patch Series S/W/F Date Submitter Delegate State
[v4,16/16] target/riscv: Compute mstatus.sd on demand target/riscv: Rationalize XLEN and operand length --- 2021-10-19 Richard Henderson Superseded
[v4,15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump target/riscv: Rationalize XLEN and operand length --- 2021-10-19 Richard Henderson New
[v4,14/16] target/riscv: Align gprs and fprs in cpu_dump target/riscv: Rationalize XLEN and operand length --- 2021-10-19 Richard Henderson Superseded
[v4,13/16] target/riscv: Use gen_shift*_per_ol for RVB, RVI target/riscv: Rationalize XLEN and operand length --- 2021-10-19 Richard Henderson Superseded
[v4,12/16] target/riscv: Use gen_unary_per_ol for RVB target/riscv: Rationalize XLEN and operand length --- 2021-10-19 Richard Henderson Superseded
[v4,11/16] target/riscv: Adjust trans_rev8_32 for riscv64 target/riscv: Rationalize XLEN and operand length --- 2021-10-19 Richard Henderson Superseded
[v4,10/16] target/riscv: Use gen_arith_per_ol for RVM target/riscv: Rationalize XLEN and operand length --- 2021-10-19 Richard Henderson Superseded
[v4,09/16] target/riscv: Replace DisasContext.w with DisasContext.ol target/riscv: Rationalize XLEN and operand length --- 2021-10-19 Richard Henderson Superseded
[v4,08/16] target/riscv: Replace is_32bit with get_xl/get_xlen target/riscv: Rationalize XLEN and operand length --- 2021-10-19 Richard Henderson Superseded
[v4,07/16] target/riscv: Properly check SEW in amo_op target/riscv: Rationalize XLEN and operand length --- 2021-10-19 Richard Henderson Superseded
[v4,06/16] target/riscv: Use REQUIRE_64BIT in amo_check64 target/riscv: Rationalize XLEN and operand length --- 2021-10-19 Richard Henderson Superseded
[v4,05/16] target/riscv: Add MXL/SXL/UXL to TB_FLAGS target/riscv: Rationalize XLEN and operand length --- 2021-10-19 Richard Henderson Superseded
[v4,04/16] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl target/riscv: Rationalize XLEN and operand length --- 2021-10-19 Richard Henderson Superseded
[v4,03/16] target/riscv: Split misa.mxl and misa.ext target/riscv: Rationalize XLEN and operand length --- 2021-10-19 Richard Henderson Superseded
[v4,02/16] target/riscv: Create RISCVMXL enumeration target/riscv: Rationalize XLEN and operand length --- 2021-10-19 Richard Henderson Superseded
[v4,01/16] target/riscv: Move cpu_get_tb_cpu_state out of line target/riscv: Rationalize XLEN and operand length --- 2021-10-19 Richard Henderson Superseded