Show patches with: Submitter = Alistair Francis       |    Archived = No       |   346 patches
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Patch Series S/W/F Date Submitter Delegate State
[v1,1/1] hw/intc/ibex_plic: Clear the claim register when read [v1,1/1] hw/intc/ibex_plic: Clear the claim register when read --- 2020-11-06 Alistair Francis New
[v4,4/5] target/riscv: Remove the hyp load and store functions [v4,1/5] target/riscv: Add a virtualised MMU Mode --- 2020-11-04 Alistair Francis New
[v4,1/5] target/riscv: Add a virtualised MMU Mode [v4,1/5] target/riscv: Add a virtualised MMU Mode --- 2020-11-04 Alistair Francis New
[v3,5/7] target/riscv: Remove the hyp load and store functions [v3,1/7] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit --- 2020-11-03 Alistair Francis Superseded
[v3,4/7] target/riscv: Remove the HS_TWO_STAGE flag [v3,1/7] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit --- 2020-11-03 Alistair Francis New
[v3,1/7] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit [v3,1/7] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit --- 2020-11-03 Alistair Francis Superseded
[v1,1/1] linux-user/syscall: Fix missing target_to_host_timespec64() check [v1,1/1] linux-user/syscall: Fix missing target_to_host_timespec64() check --- 2020-11-03 Alistair Francis New
[PULL,v2,19/19] target/riscv/csr.c : add space before the open parenthesis '(' Untitled series #75168 --- 2020-11-03 Alistair Francis New
[PULL,v2,14/19] hw/misc: Add Microchip PolarFire SoC SYSREG module support Untitled series #75168 --- 2020-11-03 Alistair Francis Superseded
[PULL,v2,11/19] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules Untitled series #75168 --- 2020-11-03 Alistair Francis New
[PULL,v2,10/19] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support Untitled series #75168 --- 2020-11-03 Alistair Francis New
[PULL,v2,08/19] target/riscv: Add sifive_plic vmstate Untitled series #75168 --- 2020-11-03 Alistair Francis New
[PULL,v2,07/19] target/riscv: Add V extension state description Untitled series #75168 --- 2020-11-03 Alistair Francis Superseded
[PULL,v2,06/19] target/riscv: Add H extension state description Untitled series #75168 --- 2020-11-03 Alistair Francis New
[PULL,v2,03/19] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit Untitled series #75168 --- 2020-11-03 Alistair Francis Superseded
[PULL,v2,02/19] hw/riscv: virt: Allow passing custom DTB Untitled series #75168 --- 2020-11-03 Alistair Francis Superseded
[PULL,18/18] hw/riscv: microchip_pfsoc: Hook the I2C1 controller riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,17/18] hw/riscv: microchip_pfsoc: Correct DDR memory map riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,16/18] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,15/18] hw/riscv: microchip_pfsoc: Connect the SYSREG module riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,14/18] hw/misc: Add Microchip PolarFire SoC SYSREG module support riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,13/18] hw/riscv: microchip_pfsoc: Connect the IOSCB module riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,12/18] hw/misc: Add Microchip PolarFire SoC IOSCB module support riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,11/18] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules riscv-to-apply queue --- 2020-10-29 Alistair Francis Superseded
[PULL,10/18] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support riscv-to-apply queue --- 2020-10-29 Alistair Francis Superseded
[PULL,09/18] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,08/18] target/riscv: Add sifive_plic vmstate riscv-to-apply queue --- 2020-10-29 Alistair Francis Superseded
[PULL,07/18] target/riscv: Add V extension state description riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,06/18] target/riscv: Add H extension state description riscv-to-apply queue --- 2020-10-29 Alistair Francis Superseded
[PULL,05/18] target/riscv: Add PMP state description riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,04/18] target/riscv: Add basic vmstate description of CPU riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,03/18] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,02/18] hw/riscv: virt: Allow passing custom DTB riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[v2,5/5] target/riscv: Split the Hypervisor execute load helpers Fix the Hypervisor access functions --- 2020-10-28 Alistair Francis New
[v2,4/5] target/riscv: Remove the hyp load and store functions Fix the Hypervisor access functions --- 2020-10-28 Alistair Francis New
[v2,3/5] target/riscv: Remove the HS_TWO_STAGE flag Fix the Hypervisor access functions --- 2020-10-28 Alistair Francis Superseded
[v2,2/5] target/riscv: Set the virtualised MMU mode when doing hyp accesses Fix the Hypervisor access functions --- 2020-10-28 Alistair Francis New
[v2,1/5] target/riscv: Add a virtualised MMU Mode Fix the Hypervisor access functions --- 2020-10-28 Alistair Francis New
[v1,16/16] target/riscv: Consolidate *statush registers RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,15/16] target/riscv: Convert the get/set_field() to support 64-bit values RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,14/16] target/riscv: cpu: Set XLEN independently from target RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,13/16] target/riscv: csr: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,12/16] target/riscv: cpu_helper: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,11/16] target/riscv: cpu: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,10/16] target/riscv: Specify the XLEN for CPUs RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,09/16] target/riscv: Add a riscv_cpu_is_32bit() helper function RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,08/16] target/riscv: fpu_helper: Match function defs in HELPER macros RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,07/16] hw/riscv: sifive_u: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,06/16] hw/riscv: spike: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,05/16] hw/riscv: virt: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,04/16] hw/riscv: boot: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,03/16] riscv: virt: Remove target macro conditionals RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,02/16] riscv: spike: Remove target macro conditionals RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,01/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,5/5] target/riscv: Split the Hypervisor execute load helpers Fix the Hypervisor access functions --- 2020-10-23 Alistair Francis Superseded
[v1,4/5] target/riscv: Remove the hyp load and store functions Fix the Hypervisor access functions --- 2020-10-23 Alistair Francis Superseded
[v1,3/5] target/riscv: Remove the HS_TWO_STAGE flag Fix the Hypervisor access functions --- 2020-10-23 Alistair Francis Superseded
[v1,2/5] target/riscv: Set the virtualised MMU mode when doing hyp accesses Fix the Hypervisor access functions --- 2020-10-23 Alistair Francis Superseded
[v1,1/5] target/riscv: Add a virtualised MMU Mode Fix the Hypervisor access functions --- 2020-10-23 Alistair Francis Superseded
[PULL,12/12] hw/misc/sifive_u_otp: Add backend drive support riscv-to-apply queue --- 2020-10-23 Alistair Francis New
[PULL,11/12] hw/misc/sifive_u_otp: Add write function and write-once protection riscv-to-apply queue --- 2020-10-23 Alistair Francis New
[PULL,10/12] target/riscv: raise exception to HS-mode at get_physical_address riscv-to-apply queue --- 2020-10-23 Alistair Francis New
[PULL,09/12] hw/riscv: Load the kernel after the firmware riscv-to-apply queue --- 2020-10-23 Alistair Francis Superseded
[PULL,08/12] hw/riscv: Add a riscv_is_32_bit() function riscv-to-apply queue --- 2020-10-23 Alistair Francis Superseded
[PULL,07/12] hw/riscv: Return the end address of the loaded firmware riscv-to-apply queue --- 2020-10-23 Alistair Francis Superseded
[PULL,06/12] hw/riscv: sifive_u: Allow specifying the CPU riscv-to-apply queue --- 2020-10-23 Alistair Francis Superseded
[PULL,05/12] target/riscv: Fix implementation of HLVX.WU instruction riscv-to-apply queue --- 2020-10-23 Alistair Francis New
[PULL,04/12] target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt riscv-to-apply queue --- 2020-10-23 Alistair Francis New
[PULL,03/12] target/riscv: Fix update of hstatus.SPVP riscv-to-apply queue --- 2020-10-23 Alistair Francis New
[PULL,02/12] hw/intc: Move sifive_plic.h to the include directory riscv-to-apply queue --- 2020-10-23 Alistair Francis New
[PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() riscv-to-apply queue --- 2020-10-23 Alistair Francis Superseded
[v2,4/4] hw/riscv: Load the kernel after the firmware Allow loading a no MMU kernel --- 2020-10-14 Alistair Francis New
[v2,3/4] hw/riscv: Add a riscv_is_32_bit() function Allow loading a no MMU kernel --- 2020-10-14 Alistair Francis Superseded
[v2,2/4] hw/riscv: Return the end address of the loaded firmware Allow loading a no MMU kernel --- 2020-10-14 Alistair Francis Superseded
[v2,1/4] hw/riscv: sifive_u: Allow specifying the CPU Allow loading a no MMU kernel --- 2020-10-14 Alistair Francis Superseded
[v2,1/1] register: Remove unnecessary NULL check [v2,1/1] register: Remove unnecessary NULL check --- 2020-10-02 Alistair Francis New
[v1,1/1] register: Remove unnecessary NULL check [v1,1/1] register: Remove unnecessary NULL check --- 2020-10-02 Alistair Francis New
[v1,4/4] hw/riscv: Load the kernel after the firmware Allow loading a no MMU kernel --- 2020-10-02 Alistair Francis New
[v1,3/4] hw/riscv: Add a riscv_is_32_bit() function Allow loading a no MMU kernel --- 2020-10-02 Alistair Francis New
[v1,2/4] hw/riscv: Return the end address of the loaded firmware Allow loading a no MMU kernel --- 2020-10-02 Alistair Francis New
[v1,1/4] hw/riscv: sifive_u: Allow specifying the CPU Allow loading a no MMU kernel --- 2020-10-02 Alistair Francis New
[v2,1/1] riscv: Convert interrupt logs to use qemu_log_mask() [v2,1/1] riscv: Convert interrupt logs to use qemu_log_mask() --- 2020-10-02 Alistair Francis New
[v1,1/1] riscv: Convert interrupt logs to use qemu_log_mask() [v1,1/1] riscv: Convert interrupt logs to use qemu_log_mask() --- 2020-09-27 Alistair Francis New
[PULL,2/2] core/register: Specify instance_size in the TypeInfo register queue --- 2020-09-27 Alistair Francis New
[PULL,1/2] load_elf: Remove unused address variables from callers register queue --- 2020-09-27 Alistair Francis New
[PULL,30/30] hw/riscv: Sort the Kconfig options in alphabetical order riscv-to-apply queue --- 2020-09-10 Alistair Francis New
[PULL,29/30] hw/riscv: Drop CONFIG_SIFIVE riscv-to-apply queue --- 2020-09-10 Alistair Francis New
[PULL,28/30] hw/riscv: Always build riscv_hart.c riscv-to-apply queue --- 2020-09-10 Alistair Francis New
[PULL,27/30] hw/riscv: Move sifive_test model to hw/misc riscv-to-apply queue --- 2020-09-10 Alistair Francis New
[PULL,26/30] hw/riscv: Move sifive_uart model to hw/char riscv-to-apply queue --- 2020-09-10 Alistair Francis New
[PULL,25/30] hw/riscv: Move riscv_htif model to hw/char riscv-to-apply queue --- 2020-09-10 Alistair Francis New
[PULL,24/30] hw/riscv: Move sifive_plic model to hw/intc riscv-to-apply queue --- 2020-09-10 Alistair Francis New
[PULL,23/30] hw/riscv: Move sifive_clint model to hw/intc riscv-to-apply queue --- 2020-09-10 Alistair Francis New
[PULL,22/30] hw/riscv: Move sifive_gpio model to hw/gpio riscv-to-apply queue --- 2020-09-10 Alistair Francis New
[PULL,21/30] hw/riscv: Move sifive_u_otp model to hw/misc riscv-to-apply queue --- 2020-09-10 Alistair Francis New
[PULL,20/30] hw/riscv: Move sifive_u_prci model to hw/misc riscv-to-apply queue --- 2020-09-10 Alistair Francis New
[PULL,19/30] hw/riscv: Move sifive_e_prci model to hw/misc riscv-to-apply queue --- 2020-09-10 Alistair Francis New
[PULL,18/30] hw/riscv: sifive_u: Connect a DMA controller riscv-to-apply queue --- 2020-09-10 Alistair Francis New
[PULL,17/30] hw/riscv: clint: Avoid using hard-coded timebase frequency riscv-to-apply queue --- 2020-09-10 Alistair Francis New
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