Show patches with: Submitter = Alistair Francis       |    State = Action Required       |    Archived = No       |   250 patches
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Patch Series S/W/F Date Submitter Delegate State
[PULL,05/32] riscv: Generalize CPU init routine for the imacu CPU [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register --- 2020-06-19 Alistair Francis New
[PULL,03/32] riscv: Generalize CPU init routine for the base CPU [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register --- 2020-06-19 Alistair Francis New
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register --- 2020-06-19 Alistair Francis New
[v6,1/6] riscv/opentitan: Fix the ROM size [v6,1/6] riscv/opentitan: Fix the ROM size --- 2020-06-10 Alistair Francis New
[v2,16/17] target/riscv: Return the exception from invalid CSR accesses RISC-V: Update the Hypervisor spec to v0.6.1 --- 2020-06-05 Alistair Francis New
[v2,13/17] target/riscv: Only support a single VSXL length RISC-V: Update the Hypervisor spec to v0.6.1 --- 2020-06-05 Alistair Francis New
[v2,09/17] target/riscv: Convert MSTATUS MTL to GVA RISC-V: Update the Hypervisor spec to v0.6.1 --- 2020-06-05 Alistair Francis New
[v2,08/17] target/riscv: Don't allow guest to write to htinst RISC-V: Update the Hypervisor spec to v0.6.1 --- 2020-06-05 Alistair Francis New
[v2,04/17] target/riscv: Implement checks for hfence RISC-V: Update the Hypervisor spec to v0.6.1 --- 2020-06-05 Alistair Francis New
[PULL,06/15] target/riscv: Remove the deprecated CPUs riscv-to-apply queue --- 2020-06-03 Alistair Francis New
[PULL,04/15] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions riscv-to-apply queue --- 2020-06-03 Alistair Francis New
[PULL,02/15] riscv: Change the default behavior if no -bios option is specified riscv-to-apply queue --- 2020-06-03 Alistair Francis New
[v4,4/4] docs: deprecated: Update the -bios documentation Untitled series #60268 --- 2020-05-28 Alistair Francis New
[v5,09/11] riscv/opentitan: Connect the PLIC device RISC-V Add the OpenTitan Machine --- 2020-05-28 Alistair Francis New
[v5,08/11] hw/intc: Initial commit of lowRISC Ibex PLIC RISC-V Add the OpenTitan Machine --- 2020-05-28 Alistair Francis New
[v4,10/10] target/riscv: Use a smaller guess size for no-MMU PMP [v4,01/10] riscv/boot: Add a missing header include --- 2020-05-27 Alistair Francis New
[v4,03/10] target/riscv: Disable the MMU correctly [v4,01/10] riscv/boot: Add a missing header include --- 2020-05-27 Alistair Francis New
[v3,3/3] target/riscv: Drop support for ISA spec version 1.09.1 [v3,1/3] hw/riscv: spike: Remove deprecated ISA specific machines --- 2020-05-26 Alistair Francis New
[v2,2/2] sifive_e: Support the revB machine Add support for the HiFive1 revB --- 2020-05-20 Alistair Francis New
[v3,8/9] riscv/opentitan: Connect the UART device RISC-V Add the OpenTitan Machine --- 2020-05-19 Alistair Francis New
[v3,5/9] hw/char: Initial commit of Ibex UART RISC-V Add the OpenTitan Machine --- 2020-05-19 Alistair Francis New
[v3,4/9] riscv: Initial commit of OpenTitan machine RISC-V Add the OpenTitan Machine --- 2020-05-19 Alistair Francis New
[v3,3/9] target/riscv: Add the lowRISC Ibex CPU RISC-V Add the OpenTitan Machine --- 2020-05-19 Alistair Francis New
[v1,1/2] riscv: sifive_e: Manually define the machine [v1,1/2] riscv: sifive_e: Manually define the machine --- 2020-05-14 Alistair Francis New
[v2,9/9] target/riscv: Use a smaller guess size for no-MMU PMP [v2,1/9] riscv/boot: Add a missing header include --- 2020-05-07 Alistair Francis New
[v2,7/9] riscv/opentitan: Connect the PLIC device [v2,1/9] riscv/boot: Add a missing header include --- 2020-05-07 Alistair Francis New
[v2,5/9] hw/char: Initial commit of Ibex UART [v2,1/9] riscv/boot: Add a missing header include --- 2020-05-07 Alistair Francis New
[v2,4/9] riscv: Initial commit of OpenTitan machine [v2,1/9] riscv/boot: Add a missing header include --- 2020-05-07 Alistair Francis New
[v2,1/9] riscv/boot: Add a missing header include [v2,1/9] riscv/boot: Add a missing header include --- 2020-05-07 Alistair Francis New
[v1,1/2] hw/riscv: spike: Remove deprecated ISA specific machines [v1,1/2] hw/riscv: spike: Remove deprecated ISA specific machines --- 2020-05-06 Alistair Francis New
[PULL,v2,14/14] hw/riscv/spike: Allow more than one CPUs [PULL,v2,01/14] riscv/sifive_u: Fix up file ordering --- 2020-04-29 Alistair Francis New
[PULL,v2,11/14] roms: opensbi: Upgrade from v0.6 to v0.7 [PULL,v2,01/14] riscv/sifive_u: Fix up file ordering --- 2020-04-29 Alistair Francis New
[PULL,v2,06/14] riscv: Fix Stage2 SV32 page table walk [PULL,v2,01/14] riscv/sifive_u: Fix up file ordering --- 2020-04-29 Alistair Francis New
[PULL,v2,05/14] riscv: AND stage-1 and stage-2 protection flags [PULL,v2,01/14] riscv/sifive_u: Fix up file ordering --- 2020-04-29 Alistair Francis New
[PULL,v2,01/14] riscv/sifive_u: Fix up file ordering [PULL,v2,01/14] riscv/sifive_u: Fix up file ordering --- 2020-04-29 Alistair Francis New
[PULL,13/14] hw/riscv/spike: Allow loading firmware separately using -bios option RISC-V Patch Queue for 5.1 --- 2020-04-29 Alistair Francis New
[PULL,12/14] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware() RISC-V Patch Queue for 5.1 --- 2020-04-29 Alistair Francis New
[PULL,09/14] target/riscv: Add a sifive-e34 cpu type RISC-V Patch Queue for 5.1 --- 2020-04-29 Alistair Francis New
[PULL,08/14] riscv: sifive_e: Support changing CPU type RISC-V Patch Queue for 5.1 --- 2020-04-29 Alistair Francis New
[PULL,04/14] riscv: Don't use stage-2 PTE lookup protection flags RISC-V Patch Queue for 5.1 --- 2020-04-29 Alistair Francis New
[PULL,03/14] riscv/sifive_u: Add a serial property to the sifive_u machine RISC-V Patch Queue for 5.1 --- 2020-04-29 Alistair Francis New
[v1,14/15] target/riscv: Only support little endian guests Untitled series #61170 --- 2020-04-26 Alistair Francis New
[v1,12/15] target/riscv: Update the CSRs to the v0.6 Hyp extension Untitled series #61170 --- 2020-04-26 Alistair Francis New
[v1,11/15] target/riscv: Update the Hypervisor trap return/entry Untitled series #61170 --- 2020-04-26 Alistair Francis New
[v1,10/15] target/riscv: Fix the interrupt cause code Untitled series #61170 --- 2020-04-26 Alistair Francis New
[v1,07/15] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions Untitled series #61170 --- 2020-04-26 Alistair Francis New
[v1,05/15] target/riscv: Allow setting a two-stage lookup in the virt status Untitled series #61170 --- 2020-04-26 Alistair Francis New
[v1,02/15] target/riscv: Report errors validating 2nd-stage PTEs Untitled series #61170 --- 2020-04-26 Alistair Francis New
[v1,2/8] RISC-V: Mark mstatus.fs dirty [v1,1/8] RISC-V: Split out mstatus_fs from tb_flags --- 2019-01-14 Alistair Francis New
[v1,1/8] RISC-V: Split out mstatus_fs from tb_flags [v1,1/8] RISC-V: Split out mstatus_fs from tb_flags --- 2019-01-14 Alistair Francis New
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