Show patches with: Series = [v10,01/61] target/riscv: add vector extension field in CPURISCVState       |   20 patches
Patch Series S/W/F Date Submitter Delegate State
[v10,37/61] target/riscv: vector floating-point min/max instructions [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei Superseded
[v10,35/61] target/riscv: vector widening floating-point fused multiply-add instructions [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei Superseded
[v10,33/61] target/riscv: vector widening floating-point multiply [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei Superseded
[v10,31/61] target/riscv: vector widening floating-point add/subtract instructions [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei Superseded
[v10,29/61] target/riscv: vector narrowing fixed-point clip instructions [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei New
[v10,27/61] target/riscv: vector widening saturating scaled multiply-add [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei Superseded
[v10,25/61] target/riscv: vector single-width averaging add and subtract [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei Superseded
[v10,23/61] target/riscv: vector integer merge and move instructions [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei Superseded
[v10,20/61] target/riscv: vector widening integer multiply instructions [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei New
[v10,18/61] target/riscv: vector single-width integer multiply instructions [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei Superseded
[v10,17/61] target/riscv: vector integer min/max instructions [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei New
[v10,15/61] target/riscv: vector narrowing integer right shift instructions [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei Superseded
[v10,13/61] target/riscv: vector bitwise logical instructions [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei Superseded
[v10,12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei Superseded
[v10,10/61] target/riscv: vector single-width integer add and subtract [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei New
[v10,09/61] target/riscv: add vector amo operations [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei Superseded
[v10,07/61] target/riscv: add vector index load and store instructions [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei New
[v10,05/61] target/riscv: add an internals.h header [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei Superseded
[v10,03/61] target/riscv: support vector extension csr [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei Superseded
[v10,01/61] target/riscv: add vector extension field in CPURISCVState [v10,01/61] target/riscv: add vector extension field in CPURISCVState --- 2020-06-20 LIU Zhiwei Superseded