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[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
| 35 patches
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------
Nobody
andy.doan@linaro.org
andy.doan@linaro.org
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Patch
Series
S/W/F
Date
Submitter
Delegate
State
[PULL,35/35] docs: Add documentation for the mps3-an536 board
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Not Applicable
[PULL,34/35] hw/arm/mps3r: Add remaining devices
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,33/35] hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,32/35] hw/arm/mps3r: Add UARTs
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,31/35] hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,30/35] hw/arm/mps3r: Initial skeleton for mps3-an536 board
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Not Applicable
[PULL,29/35] hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,28/35] hw/misc/mps2-scc: Factor out which-board conditionals
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,27/35] hw/misc/mps2-scc: Fix condition for CFG3 register
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,26/35] target/arm: Allow access to SPSR_hyp from hyp mode
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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-
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2024-02-15
Peter Maydell
Accepted
[PULL,25/35] target/arm: Add Cortex-R52 IMPDEF sysregs
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Not Applicable
[PULL,24/35] target/arm: The Cortex-R52 has a read-only CBAR
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,23/35] target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,22/35] hw/arm/stellaris: Add missing QOM 'SoC' parent
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,21/35] hw/arm/stellaris: Add missing QOM 'machine' parent
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,20/35] hw/arm/stellaris: Convert I2C controller to Resettable interface
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,19/35] hw/arm/stellaris: Convert ADC controller to Resettable interface
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,18/35] hw/arm/smmuv3: add support for stage 1 access fault
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Not Applicable
[PULL,17/35] tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Not Applicable
[PULL,16/35] target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,15/35] tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,14/35] hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,13/35] tests/qtest/bios-tables-tests: Update virt golden reference
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Superseded
[PULL,12/35] hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Not Applicable
[PULL,11/35] tests/qtest/bios-tables-test: Allow changes to virt GTDT
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,10/35] tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,09/35] hw/block/tc58128: Don't emit deprecation warning under qtest
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,08/35] hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Not Applicable
[PULL,07/35] target/arm: Fix SVE/SME gross MTE suppression checks
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,06/35] target/arm: Handle mte in do_ldrq, do_ldro
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,05/35] target/arm: Split out make_svemte_desc
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,04/35] target/arm: Adjust and validate mtedesc sizem1
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,03/35] target/arm: Fix nregs computation in do_{ld,st}_zpa
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,02/35] linux-user/aarch64: Choose SYNC as the preferred MTE mode
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
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2024-02-15
Peter Maydell
Accepted
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
[PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
-
-
-
2024-02-15
Peter Maydell
Accepted